摘要:
A system is provided to enable leakage current measurement or parametric tests to be performed with an isolation buffer provided in a channel line. Multiple such isolation buffers are used to connect a single signal channel to multiple lines. Leakage current measurement is provided by providing a buffer bypass element, such as a resistor or transmission gate, between the input and output of each buffer. The buffer bypass element can be used to calibrate buffer delay out of the test system by using TDR measurements to determine the buffer delay based on reflected pulses through the buffer bypass element. Buffer delay can likewise be calibrated out by comparing measurements of a buffered and non-buffered channel line, or by measuring a device having a known delay.
摘要:
An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device.
摘要:
Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.
摘要:
A method of optimizing the frequency response of an interconnect system of the type which conveys high frequency signals between bond pads of separate integrated circuits (ICs) mounted on a printed circuit board (PCB) through inductive conductors, such as bond wires and package legs, and a trace on the surface of the PCB. To improve the interconnect system, capacitance is added to the trace and inductance is added to the conductors, with the added trace capacitance and conductor inductance being appropriately sized relative to one another and to various other interconnect system impedances to optimize the interconnect system impedance matching frequency response.
摘要:
A probe card of a wafer test system includes one or more programmable Ics , such as FPGAS (150), to provide routing from individual test signal channels to one of multiple probes (16). The programmable ICs can be placed on a base PCB (30) of the probe card, or on a daughtercard (100) attached to the probe card. With programmability, the PCB (30) can be used to switch limited test system channels away from unused probes (16). Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program. Because the programmable IC (150) typically includes buffers that introduce an unknown delay, in one embodiment measurement of the delay is accomplished by first programming the programmable IC (150) to provide a loop back path to the test system so that buffer delay can be measured, and then reprogramming the programmable IC (150) now with a known delay to connect to a device being tested.
摘要:
A series of pulses may be driven down each drive channel ('A', and 514, 516, 518, Fig. 5), which creates a series of composite pulses at the output of the buffer (532). Each composite pulse is a composition of the individual pulses driven down the drive channels. Timing offsets associated with the drive channels may be adjusted (406) until the individual pulses of the composite pulse align or closely align. Those timing offsets calibrate and/or deskew the drive channels, compensating for differences in the propagation delays through the drive channels. The composite pulse may be feed back to the tester through compare channels (544 and 546), and offsets associated with compare signals for each compare channel may be aligned to the composite pulse, which calibrates and/or deskews the compare channels.
摘要:
A base controller (210) disposed in a test cassette (110) receives test data for testing a plurality of electronic devices (236a,236b). The base controller wirelessly transmits the test data to a plurality of wireless test control chips (214a,214b,214c,214d,214e,214f,214g), which write the test data to each of the electronic devices. The wireless test control chips (214a,214b,214c,214d,214e,214f,214g), then read response data generated by the electronic devices (236a, 236b), and the wireless test control chips wirelessly transmit the response data to the base controller (210).
摘要:
A multiple integrated circuit (IC) die assembly (89) includes a base IC die (82) and secondary IC dice (84-86) mounted on a surface of the base IC die (82). A set of protruding contacts formed on the surface of the base IC die (82) and extending beyond the secondary IC dice link the surface of the base IC die (82) to a printed circuit board (PCB) substrate (98) with the secondary IC die (84-86) residing between the base IC (82) die and the PCB substrate (98).
摘要:
An electronic device tester channel transmits a single test signal to multiple terminals of electronic devices under test (DUTs) through a set of isolation resistors. The tester channel employs feedback to automatically adjust the test signal voltage to compensate for affects of faults at any of the DUT terminals to prevent the faults from substantially affecting the test signal voltage.
摘要:
A multiple integrated circuit (IC) die assembly (89) includes a base IC die (82) and secondary IC dice (84-86) mounted on a surface of the base IC die (82). A set of protruding contacts formed on the surface of the base IC die (82) and extending beyond the secondary IC dice link the surface of the base IC die (82) to a printed circuit board (PCB) substrate (98) with the secondary IC die (84-86) residing between the base IC (82) die and the PCB substrate (98).