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公开(公告)号：EP2856471A4
公开(公告)日：2015-11-18
申请号：EP12877868
申请日：2012-05-31
发明人： UDIPI ANIRUDDHA NAGENDRAN , MURALIMANOHAR NAVEEN , JOUPPI NORMAN PAUL , DAVIS ALAN LYNN , BALASUBRAMONIAN RAJEEV
CPC分类号： G06F11/1064 , G06F11/1012 , G06F11/1044 , G06F11/108 , G11C2029/0411
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公开(公告)号：EP2529312A4
公开(公告)日：2013-07-03
申请号：EP11737662
申请日：2011-01-27
CPC分类号： G06F13/161 , G06F12/0804 , G06F13/1642
摘要： A disclosed example apparatus includes an interface (702, 726) to receive a request to access a memory (602a) of a memory module (600) and a data store status monitor (730) to determine a status of the memory. The example apparatus also includes a message output subsystem (732) to, when the memory is busy, respond to the request with a negative acknowledgement indicating that the request to access the memory is not grantable.
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公开(公告)号：EP2891069A4
公开(公告)日：2016-02-10
申请号：EP12883648
申请日：2012-08-28
发明人： LI SHENG , YOON DOE HYUN , JOUPPI NORMAN PAUL
CPC分类号： G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F11/1471 , G06F12/0891 , G06F2003/0691 , G06F2212/1032 , G06F2212/202 , G06F2212/222 , G06F2212/251 , G06F2212/304 , G11C16/06
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公开(公告)号：EP2529374A4
公开(公告)日：2014-04-02
申请号：EP11737663
申请日：2011-01-27
发明人： MURALIMANOHAR NAVEEN , UDIPI ANIRUDDHA NAGENDRAN , CHATTERJEE NILADRISH , BALASUBRAMONIAN RAJEEV , DAVIS ALAN LYNN , JOUPPI NORMAN PAUL
IPC分类号： G11C11/4063 , G06F12/00 , G11C7/10
CPC分类号： G06F3/0625 , G06F3/0634 , G06F3/0658 , G06F3/0673 , G06F11/1088 , G06F12/0802 , G06F12/0893 , G06F2212/1028 , G06F2212/3042 , G06F2212/305 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/4082 , Y02B60/1225 , Y02D10/13
摘要： An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.
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公开(公告)号：EP2517058A4
公开(公告)日：2016-03-30
申请号：EP09852671
申请日：2009-12-21
发明人： TAN MICHAEL RENNE TY , BINKERT NATHAN LORENZO , JOUPPI NORMAN PAUL , MCLAREN MORAY , AHN JUNG HO
CPC分类号： G02B6/43 , G02B6/351 , G02B6/3556 , G02B6/3596 , G02B6/3598
摘要： A circuit switched optical interconnection fabric includes a first hollow metal waveguide and a second hollow metal waveguide which intersects the first hollow metal waveguide to form an intersection. An optical element within the intersection is configured to selectively direct an optical signal between the first hollow metal waveguide and a second hollow metal waveguide.
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公开(公告)号：EP2867897A4
公开(公告)日：2016-02-17
申请号：EP12880177
申请日：2012-06-28
CPC分类号： G11C11/5678 , G11C7/1057 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/06 , G11C16/26 , G11C2211/5642
摘要： A multi-level cell memory includes a memory cell that stores two or more bits of information; a sensing circuit coupled to the memory cell; and a row buffer structure comprising a split page buffer having a first page buffer and a second page buffer. The sensing circuit operates to read from the memory cell, places a first bit in one of the first page buffer and the second page buffer, and places the second bit in one of the first page buffer and the second page buffer.
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公开(公告)号：EP2203768A4
公开(公告)日：2015-06-03
申请号：EP08841755
申请日：2008-10-23
发明人： BEAUSOLEIL RAYMOND G , FIORENTINO MARCO , JOUPPI NORMAN PAUL , BINKERT NATHAN LORENZO , SCHREIBER ROBERT SAMUEL , XU QIANFAN
IPC分类号： G02B6/12
CPC分类号： G02B6/43 , H04B10/801
摘要： Various embodiments of the present invention are directed to photonic interconnects that can be used for on-chip as well as off-chip communications between computer system components. In one embodiment of the present invention, a photonic interconnect comprises a plurality of on-chip waveguides. Additionally, the photonic interconnect may include a plurality of off-chip waveguides, and at least one optoelectronic converter. The at least one optoelectronic converter can be photonically coupled to a portion of the plurality of on-chip waveguides, can be photonically coupled to a portion of the plurality of off-chip waveguides, and is in electronic communication with at least one computer system component.
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公开(公告)号：EP2686774A4
公开(公告)日：2014-08-20
申请号：EP11860733
申请日：2011-03-14
发明人： UDIPI ANIRUDDHA NAGENDRAN , MURALIMANOHAR NAVEEN , JOUPPI NORMAN PAUL , BALASUBRAMONIAN RAJEEV , DAVIS ALAN LYNN
CPC分类号： G06F13/3625 , G06F13/1605 , G06F13/1689
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公开(公告)号：EP2499667A4
公开(公告)日：2014-03-05
申请号：EP09851339
申请日：2009-11-13
IPC分类号： H01L23/043 , G06F11/14 , G11C5/02 , G11C5/04 , G11C7/10 , G11C8/12 , G11C11/408 , G11C11/4096 , H01L25/065
CPC分类号： G11C5/02 , G11C5/04 , G11C7/1069 , G11C7/1078 , G11C8/12 , G11C11/4087 , G11C11/4096 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.
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