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1.发明公开
公开(公告)号：EP4432354A2
公开(公告)日：2024-09-18
申请号：EP24192356.4
申请日：2017-03-06
申请人： Apple Inc.
发明人： BISWAS, Sukalpa , NEMATI, Farid
IPC分类号： H01L25/10
CPC分类号： G11C5/04 , G11C5/063 , H01L2224/1614520130101 , H01L2224/1622520130101 , H01L2924/1531120130101 , H01L25/105 , H01L25/0652 , H01L25/0657 , H01L2225/0651320130101 , H01L2225/0651720130101 , H01L2225/0654120130101 , G11C7/10 , G11C11/4093 , G11C2207/10520130101 , G11C2207/10820130101 , H01L2224/13120130101 , Y02D10/00
摘要： In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.
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公开(公告)号：EP4340023A3
公开(公告)日：2024-06-12
申请号：EP23220590.6
申请日：2020-02-03
申请人： INTEL Corporation
IPC分类号： H01L23/38 , H01L23/538
CPC分类号： H01L23/5389 , H01L23/38 , H01L23/49827 , H01L23/49816 , H01L23/49811 , H01L25/0652 , H01L2225/0651720130101 , H01L2225/0654820130101 , H01L2225/0657220130101 , H01L2225/0652720130101 , H01L2225/0655520130101 , H01L2225/0654120130101 , H01L2225/0651320130101 , H01L25/18 , H01L2224/8120320130101 , H01L2224/8181520130101 , H01L2224/7320420130101 , H01L2224/1626520130101 , H01L2224/1718120130101 , H01L2924/1015820130101 , H01L2224/1623820130101 , H01L2924/1515320130101 , H01L2924/1816120130101 , H01L24/16 , H01L2224/1614520130101 , H01L2224/13120130101 , H01L2224/1302520130101 , H01L23/147 , H01L21/486 , H01L23/5385
摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
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公开(公告)号：EP4376002A1
公开(公告)日：2024-05-29
申请号：EP23192340.0
申请日：2023-08-21
发明人： YANG, Yunseok , LEE, Eungchang , RYU, Seula , AN, Minhwan , JEONG, Yunkyeong , CHOO, Chul-Hwan
IPC分类号： G11C5/02 , H01L25/065
CPC分类号： G11C5/025 , G11C8/12 , H01L25/0652 , H01L25/18 , H01L2225/0654120130101 , H01L2225/0651320130101 , H01L25/105 , H01L2225/105820130101 , H01L23/49822 , H01L2225/0651720130101
摘要： A memory device includes a base die that includes a data signal bump configured to receive a data signal, a first memory stack that includes first memory dies sequentially stacked on the base die, and a second memory stack that includes second memory dies sequentially stacked on the base die and spaced from the first memory stack in a direction parallel to an upper surface of the base die. The base die is configured to selectively provide the data signal received through the data signal bump to one of the first memory stack or the second memory stack based on a selection signal.
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公开(公告)号：EP3866193B1
公开(公告)日：2024-10-09
申请号：EP20205957.2
申请日：2020-11-05
IPC分类号： H01L25/16 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/18
CPC分类号： H01L2224/7325320130101 , H01L24/16 , H01L24/32 , H01L2224/3214520130101 , H01L23/49811 , H01L2224/1622720130101 , H01L2224/1210520130101 , H01L2924/1531120130101 , H01L2224/7320320130101 , H01L2224/7321720130101 , H01L2225/0654120130101 , H01L2225/0652420130101 , H01L2225/0656820130101 , H01L2225/0658920130101 , H01L24/20 , H01L24/73 , H01L25/18 , H01L25/0657 , H01L2225/0651720130101 , H01L2225/0654820130101
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公开(公告)号：EP4397152A1
公开(公告)日：2024-07-10
申请号：EP22865235.0
申请日：2022-05-08
发明人： YANG, Xiang , DUTTA, Deepanshu
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公开(公告)号：EP4325552A3
公开(公告)日：2024-07-10
申请号：EP23219820.0
申请日：2019-05-03
申请人： Intel Corporation
发明人： SANKMAN, Robert , AGRGHARAM, Sairam , WANG, Guotao , OU, Shengquan , DE BONIS, Thomas , SPENCER, Todd , SUN, Yang
IPC分类号： H01L21/60 , H01L25/065 , H01L21/98 , H01L21/56 , H01L23/31 , H01L23/538
CPC分类号： H01L23/3128 , H01L23/3135 , H01L21/56 , H01L21/568 , H01L23/5385 , H01L23/49816 , H01L23/5389 , H01L25/0655 , H01L2224/132920130101 , H01L2224/13320130101 , H01L2224/0822520130101 , H01L2224/0410520130101 , H01L2224/920220130101 , H01L2224/1210520130101 , H01L2224/9720130101 , H01L2224/1622720130101 , H01L2224/8198620130101 , H01L24/95 , H01L24/81 , H01L24/16 , H01L24/17 , H01L2224/8119220130101 , H01L2224/8119120130101 , H01L2224/170320130101 , H01L2224/8100520130101 , H01L2224/9500120130101 , H01L2224/3224520130101 , H01L2224/7325320130101 , H01L2224/7320920130101 , H01L2924/1816220130101 , H01L2924/1816120130101 , H01L24/96 , H01L2224/7320420130101 , H01L2224/3222520130101 , H01L25/0652 , H01L2224/0618120130101 , H01L2224/055720130101 , H01L2225/0651320130101 , H01L2225/0651720130101 , H01L2225/0654120130101 , H01L2225/0656220130101 , H01L2225/0658620130101 , H01L2224/0814520130101 , H01L2224/1614520130101 , H01L2924/1625120130101 , H01L2224/8203920130101 , H01L2223/5442620130101 , H01L2224/9222420130101 , H01L24/19 , H01L2924/1519220130101 , H01L25/50 , H01L2224/13120130101 , H01L2224/7325120130101 , H01L2224/040120130101 , H01L2224/1718120130101 , H01L24/73 , H01L24/08
摘要： An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
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公开(公告)号：EP4393013A1
公开(公告)日：2024-07-03
申请号：EP22748695.8
申请日：2022-07-01
发明人： VEMURI, Krishna , KIM, Jinseong
IPC分类号： H01L23/538 , H01L25/065 , H01L23/48 , H01L23/00 , H01L25/00 , H01L25/18
CPC分类号： H01L23/5383 , H01L23/5385 , H01L25/0657 , H01L25/50 , H01L2225/065120130101 , H01L2225/0651720130101 , H01L2225/065220130101 , H01L2225/0652420130101 , H01L2225/0654820130101 , H01L2225/0656220130101 , H01L24/16 , H01L25/18 , H01L2224/1622720130101 , H01L2224/4822720130101 , H01L2224/3214520130101 , H01L2224/7325320130101 , H01L2224/7326520130101 , H01L2924/1531120130101 , H01L2924/1519220130101 , H01L2224/9224720130101 , H01L2224/7321520130101 , H01L2224/4809120130101 , H01L2924/1420130101 , H01L2924/0001420130101 , H01L2224/1310120130101 , H01L24/13 , H01L24/48 , H01L2924/18120130101 , H01L2224/291920130101 , H01L24/29 , H01L24/83 , H01L2224/838520130101 , H01L2224/8320320130101 , H01L24/73 , H01L24/32 , H01L23/49816
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公开(公告)号：EP4391057A1
公开(公告)日：2024-06-26
申请号：EP23208916.9
申请日：2023-11-09
发明人： CHO, Yongeun , KIM, Kibum , KIM, Seonkyeong , KIM, Hayoung , ROH, Hyunjeong
IPC分类号： H01L27/02 , H01L25/065 , H01L23/60
CPC分类号： H01L27/0296 , H01L27/0292 , H01L27/0207 , H01L23/60 , H01L25/0657 , H01L25/18 , H01L2225/0651320130101 , H01L2225/0651720130101 , H01L2225/0654120130101
摘要： A semiconductor device may include a substrate including a Keep-Out Zone (KOZ) and a layout finishing cell region, a through silicon via (TSV) penetrating the substrate and surrounded by the KOZ; an ESD diode on an upper surface of the substrate, a driver circuit, gate structures, and metal wirings electrically connecting the TSV, the ESD diode, and the driver circuit. The layout finishing cell region may surround the KOZ and the ESD diode. The driver circuit may be adjacent to and outside the layout finishing cell region. The substrate may include active regions extending from an end inside the layout finishing cell region. The gate structures may intersect the active regions to form semiconductor components. The driver circuit may include at least some of the semiconductor components.
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公开(公告)号：EP4379798A1
公开(公告)日：2024-06-05
申请号：EP23192380.6
申请日：2023-08-21
IPC分类号： H01L23/538 , H01L21/56 , H01L23/498
CPC分类号： H01L25/0652 , H01L23/5385 , H01L23/13 , H01L23/49816 , H01L23/5386 , H01L23/49811 , H01L2224/8120130101 , H01L23/3128 , H01L21/56 , H01L2225/0651720130101 , H01L2225/065220130101 , H01L2225/0657220130101 , H01L2225/0658220130101 , H01L2225/0658620130101 , H01L2225/0655520130101 , H01L2225/0652720130101
摘要： Semiconductor packages and methods of fabricating the same are provided. The semiconductor package includes a first package substrate including a first area, a first semiconductor chip mounted on the first area, a second package substrate disposed on an upper surface of the first semiconductor chip and including a second area and a first hole penetrating through the second area, a second semiconductor chip mounted on the second area, a connection member electrically connecting the first package substrate and the second package substrate and between the first package substrate and the second package substrate, and a mold film covering the second semiconductor chip on the second package substrate, filling the first hole, and covering the first semiconductor chip and the connection member on the first package substrate.
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10.发明公开
公开(公告)号：EP4427269A1
公开(公告)日：2024-09-11
申请号：EP22887944.1
申请日：2022-10-17
发明人： PAREKH, Kunal, R.
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31
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