公开(公告)号：EP1429590A4

公开(公告)日：2007-07-11

申请号：EP02765602

申请日：2002-09-19

Applicant: SONY CORP

Inventor： OGAWA TSUYOSHI

IPC: H05K3/38 ,  H05K3/46 ,  H01L23/12 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16 ,  H05K1/16 ,  H05K3/06

CPC classification number: H01L23/49894 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/498 ,  H01L23/49822 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K3/062 ,  H05K3/067 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2203/0315 ,  H05K2203/0361 ,  H05K2203/1453 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A thin film circuit board device having passive elements in a wiring layer comprises a base substrate (2) and a circuit section (3) with insulation layers (11) (16) pattern wirings (14) (17) formed on a build-up face (2a), and a receiving electrode section (21) on the first insulation layer (11), and with a passive element electrically connected to the receiving electrode section (21). The circuit section (3) comprises a substrate layer (23) and substrate titanium layer (22) formed by so stacking a substrate titanium film and substrate film as to coat the receiving electrode section (21) and each passive element, and by etching the substrate film and substrate titanium film in a region free of the metal film with a mask of a metal film of the first pattern wiring (14) formed on the substrate film. Thus, the substrate titanium film serving as the substrate titanium layer (22) prevents the receiving electrode section and each passive element from being corroded by an etchant, so that a high-performance passive element is constituted.

公开(公告)号：EP1519414A4

公开(公告)日：2009-03-04

申请号：EP03733511

申请日：2003-06-19

Applicant: SONY CORP

Inventor： OGAWA TSUYOSHI

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H01L25/04 ,  H01L25/18 ,  H05K3/00 ,  H05K3/20 ,  H05K3/28 ,  H05K3/42 ,  H05K3/46 ,  H01L23/52

CPC classification number: H01L23/3121 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5389 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/0023 ,  H05K3/0058 ,  H05K3/205 ,  H05K3/284 ,  H05K3/423 ,  H05K3/465 ,  H05K3/4682 ,  H05K2203/025 ,  H05K2203/0733

Abstract: A multilayer wiring circuit module comprising a plurality of unit wiring layers subjected to interlayer connection through a large number of via holes. In each unit wiring layer (8)-(12), via hole grooves (25) are made in a first insulation layer (22) formed of a photosensitive insulating resin material by photolithographic processing, and wiring grooves (27) are made in a second insulation layer (23) formed of a photosensitive insulating resin material on the first insulation layer (22) by photolithographic processing. A conductor metal layer (24) is formed on the second insulation layer (23) such that the via hole grooves (25) and the wiring grooves (27) are filled with the conductor metal. The conductor metal layer (24) is subjected to polishing until the major surface of the second insulation layer (23) is exposed, and via holes (13) and a wiring pattern (26) are formed of the conductor metal filling the via hole grooves (25) and the wiring grooves (27).