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公开(公告)号：EP2863440A1
公开(公告)日：2015-04-22
申请号：EP13804906.9
申请日：2013-06-06
发明人： TAKEUCHI, Yuichi , SUZUKI, Naohiro , SOEJIMA, Narumasa , WATANABE, Yukihiko , SUGIMOTO, Masahiro , TAKAYA, Hidefumi , SOENO, Akitaka , MORIMOTO, Jun
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L27/04 , H01L29/06 , H01L29/12 , H01L29/47 , H01L29/861 , H01L29/868 , H01L29/872
CPC分类号： H01L29/7811 , H01L21/046 , H01L21/0475 , H01L21/30604 , H01L21/308 , H01L21/761 , H01L21/8213 , H01L29/0615 , H01L29/063 , H01L29/0634 , H01L29/0661 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/157 , H01L29/158 , H01L29/1608 , H01L29/41766 , H01L29/4236 , H01L29/66068 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7813 , H01L29/861 , H01L29/872
摘要： An SiC semiconductor device has a p type region (5) including a low concentration region (5b) and a high concentration region (5c) filled in a trench (5a) formed in a cell region. A p type column is provided by the low concentration region (5b), and a p + type deep layer is provided by the high concentration region (5c). Thus, since a SJ structure can be made by the p type column provided by the low concentration region (5b) and the n type column provided by the n type drift layer (2), an on-state resistance can be reduced. Since a drain potential can be blocked by the p + type deep layer provided by the high concentration region (5c), at a time of turning off, an electric field applied to the gate insulation film (8) can be alleviated and thus breakage of the gate insulation film (8) can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film (8).
摘要翻译： SiC半导体器件具有包括填充在单元区域中形成的沟槽（5a）中的低浓度区域（5b）和高浓度区域（5c）的p型区域（5）。 低浓度区（5b）提供p型柱，高浓度区（5c）提供p +型深层。 因此，由于可以通过由低浓度区域（5b）提供的p型列和由n型漂移层（2）提供的n型列来形成SJ结构，所以可以降低导通电阻。 由于漏极电位能够被高浓度区域（5c）提供的p +型深层阻挡，所以在关断时，可以减轻施加到栅极绝缘膜（8）的电场，并因此破坏 栅绝缘膜（8）可以被限制。 因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜（8）的断裂限制。
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公开(公告)号：EP1779438B2
公开(公告)日：2019-07-31
申请号：EP05755884.3
申请日：2005-06-22
发明人： SUGIMOTO, Masahiro , KACHI, Tetsu , NAKANO, Yoshitaka , UESUGI, Tsutomu , UEDA, Hiroyuki , SOEJIMA, Narumasa
IPC分类号： H01L29/778 , H01L21/335
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公开(公告)号：EP2883239B1
公开(公告)日：2017-10-25
申请号：EP13802420.3
申请日：2013-09-24
IPC分类号： H01L21/04
CPC分类号： H01L21/0485 , H01L21/30604 , H01L21/32133
摘要： A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.
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公开(公告)号：EP2883239B8
公开(公告)日：2018-02-14
申请号：EP13802420.3
申请日：2013-09-24
IPC分类号： H01L21/04
CPC分类号： H01L21/0485 , H01L21/30604 , H01L21/32133
摘要： A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.
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5.发明公开NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开VERFAHREN ZU SEINER HERSTELLUNG的NITRID-HALBLEITERBAUEMENT
公开(公告)号：EP2405467A1
公开(公告)日：2012-01-11
申请号：EP09841075.6
申请日：2009-03-02
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/41766 , H01L29/66462 , H01L29/7788
摘要： Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device (100), which is a vertical HEMT, is provided with an n - type GaN first nitride semiconductor layer (2), p + type GaN second nitride semiconductor layers (6a, 6b), an n - type GaN third nitride semiconductor layer (9), and an n - type AIGaN fourth nitride semiconductor layer (8) that is in hetero junction with a front surface of the third nitride semiconductor layer (9). Openings (11a, 11b) that penetrate the third nitride semiconductor layer (9) and reach front surfaces of the second nitride semiconductor layers (6a, 6b) are provided at positions isolated from the peripheral edge of the third nitride semiconductor layer (9). Source electrodes (12a, 12b) are provided in the openings (11a, 11b). Etching damage (7b) that is in contact with the source electrodes (12a, 12b) is surrounded by a region where no etching damage is formed.
摘要翻译： 提供了可以抑制泄漏电流的发生的垂直氮化物半导体器件，以及这种氮化物半导体器件的制造方法。 作为垂直HEMT的氮化物半导体器件（100）具有n型GaN第一氮化物半导体层（2），p +型GaN第二氮化物半导体层（6a，6b），n型GaN第三 氮化物半导体层（9）和与第三氮化物半导体层（9）的前表面异质结的n型AIGaN第四氮化物半导体层（8）。 穿过第三氮化物半导体层（9）并到达第二氮化物半导体层（6a，6b）的前表面的开口（11a，11b）设置在与第三氮化物半导体层（9）的周边隔离的位置。 源电极（12a，12b）设置在开口（11a，11b）中。 与源电极（12a，12b）接触的蚀刻损伤（7b）被没有形成蚀刻损伤的区域包围。
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公开(公告)号：EP1815523B1
公开(公告)日：2016-09-14
申请号：EP05828962.0
申请日：2005-11-14
IPC分类号： H01L29/812 , H01L29/78 , H01L29/778 , H01L29/06 , H01L29/08 , H01L29/20 , H01L29/41
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/0692 , H01L29/0696 , H01L29/0843 , H01L29/0847 , H01L29/0891 , H01L29/2003 , H01L29/41 , H01L29/778 , H01L29/7788 , H01L29/8122
摘要： A semiconductor device is provided with a drain electrode 22, a semiconductor base plate 32, an electric current regulation layer 42 covering a part of a surface of the semiconductor base plate 32 and leaving a non-covered surface 55 at the surface of the semiconductor base plate 32, a semiconductor layer 50 covering a surface of the electric current regulation layer 42, and a source electrode 62 formed at a surface of the semiconductor layer 50. A drift region 56, a channel forming region 54, and a source region 52 are formed within the semiconductor layer 50. The drain electrode 22 is connected to a first terminal of a power source, and the source electrode 62 is connected to a second terminal of the power source. With this semiconductor layer 50, it is possible to increase withstand voltage or reduce the occurrence of current leakage.
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公开(公告)号：EP2883239A2
公开(公告)日：2015-06-17
申请号：EP13802420.3
申请日：2013-09-24
IPC分类号： H01L21/04
CPC分类号： H01L21/0485 , H01L21/30604 , H01L21/32133
摘要： A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate (4); widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming, an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.
摘要翻译： 一种半导体器件的制造方法，包括：通过在SiC半导体衬底（4）的表面上的绝缘层的开口的内侧上沉积作为电极材料的金属来形成电金属层; 通过在形成电极金属层之后刻蚀绝缘层来扩大形成在绝缘层中的开口中的内壁表面和电极金属层之间的间隙; 以及在绝缘层被蚀刻之后，通过加热SiC半导体基板和金属电极层，在电极金属层和SiC半导体基板之间形成欧姆接触。
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公开(公告)号：EP2863417A1
公开(公告)日：2015-04-22
申请号：EP13804396.3
申请日：2013-06-06
IPC分类号： H01L21/336 , H01L29/06 , H01L29/12 , H01L29/78
CPC分类号： H01L29/66068 , H01L21/02529 , H01L21/0455 , H01L21/0475 , H01L21/049 , H01L21/3065 , H01L29/045 , H01L29/0619 , H01L29/0623 , H01L29/0661 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7827
摘要： In a method for producing an SiC semiconductor device, a p type layer (31) is formed in a trench (6) by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer (7). That is, a portion of the p type layer (31) formed on a side surface of the trench (6) is removed. Thus, the p type SiC layer (7) can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer (7) from remaining on the side surface of the trench (6). Accordingly, it is possible to produce an SiC semiconductor device that can achieve both high withstand voltage and high switching speed.
摘要翻译： 在用于制造SiC半导体器件的方法中，通过外延生长在沟槽（6）中形成p型层（31），然后通过氢蚀刻仅留在沟槽的底部和端部上，从而形成p 型SiC层（7）。 即，形成在沟槽（6）的侧表面上的p型层（31）的一部分被去除。 因此，可以在不依赖于对角离子注入的情况下形成p型SiC层（7）。 由于不需要单独进行对角线离子注入，因此由于转移到离子注入装置而使生产过程变得复杂的可能性较小，因此制造成本降低。 由于没有因离子注入引起的缺陷而造成损坏，所以可以减少漏极泄漏并且可靠地限制p型SiC层（7）保留在沟槽（6）的侧表面上。 因此，可以制造既能实现高耐压又能实现高开关速度的SiC半导体器件。
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公开(公告)号：EP1842238B1
公开(公告)日：2010-07-21
申请号：EP06701454.8
申请日：2006-01-20
IPC分类号： H01L29/778 , H01L29/45 , H01L29/423 , H01L21/335 , H01L29/20
CPC分类号： H01L29/452 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7787
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公开(公告)号：EP1842238A2
公开(公告)日：2007-10-10
申请号：EP06701454.8
申请日：2006-01-20
IPC分类号： H01L29/778
CPC分类号： H01L29/452 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device 10 comprises a heterojunction between a lower semiconductor layer 26 made of p-type gallium nitride and an upper semiconductor layer 28 made of n-type AlGaN, wherein the upper semiconductor layer 28 has a larger band gap than the lower semiconductor layer 26. The semiconductor device 10 further comprises a drain electrode 32 formed on a portion of a top surface of the upper semiconductor layer 28, a source electrode 34 formed on a different portion of the top surface of the upper semiconductor layer 28, and a gate electrode 36 electrically connected to the lower semiconductor layer 26. The semiconductor device 10 can operate as normally-off.
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