公开(公告)号：EP4432332A1

公开(公告)日：2024-09-18

申请号：EP24163222.3

申请日：2024-03-13

Applicant: Flosfia Inc.

Inventor： Ando, Hiroyuki ,  Tsukamoto, Naoyuki ,  Kato, Yuji

IPC: H01L21/36

CPC classification number: H01L21/02414 ,  H01L21/0243 ,  H01L21/02483 ,  H01L21/02494 ,  H01L21/02565 ,  H01L21/02433 ,  H01L21/0242 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02636

Abstract: The present disclosure provides a laminated structure suitable for semiconductor elements.
The laminated structure includes a first oxide layer having a trench structure on its surface and a second oxide layer laminated along the trench structure. A difference in thickness between centers of a bottom and a sidewall of the second oxide layer is less than 30%.

公开(公告)号：EP3050110A4

公开(公告)日：2017-05-17

申请号：EP13894791

申请日：2013-09-25

Applicant: INTEL CORP

Inventor： DASGUPTA SANSAPTAK ,  THEN HAN WUI ,  GARDNER SANAZ ,  CHU-KUNG BENJAMIN ,  RADOSAVLJEVIC MARKO ,  SUNG SEUNG HOON ,  CHAU ROBERT

IPC: H01L29/778 ,  H01L21/20 ,  H01L21/336 ,  H01L29/06 ,  H01L29/20 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/0254 ,  H01L27/10826 ,  H01L27/10879 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78618 ,  H01L29/78681

Abstract: Methods of forming high voltage (111) silicon nano-structures are described. Those methods and structures may include forming a III-V device layer on (111) surface of a silicon fin structure, forming a 2DEG inducing polarization layer on the III-V device layer, forming a source/drain material on a portion of the III-V device layer on terminal ends of the silicon fin. A middle portion of the silicon fin structure between the source and drain regions may be removed, and backfilled with a dielectric material, and then a gate dielectric and a gate material may be formed on the III-V device layer.

Abstract translation: 描述了形成高电压（111）硅纳米结构的方法。 那些方法和结构可以包括在硅鳍片结构的（111）表面上形成III-V器件层，在III-V器件层上形成2DEG诱导偏振层，在III部分III上形成源极/漏极材料 -V器件层在硅鳍的末端上。 可以去除源极和漏极区域之间的硅鳍状结构的中间部分，并用电介质材料回填，然后可以在III-V器件层上形成栅极电介质和栅极材料。

公开(公告)号：EP2948987A1

公开(公告)日：2015-12-02

申请号：EP14701369.2

申请日：2014-01-24

Applicant: Centre National de la Recherche Scientifique (C.N.R.S.)

Inventor： NATAF, Gilles ,  DE MIERRY, Philippe ,  CHENOT, Sébastien

IPC: H01L33/00 ,  H01L33/06 ,  H01L33/08 ,  H01L21/02

CPC classification number: H01L33/06 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L33/0075 ,  H01L33/08

Abstract: The invention relates to a method for the production of a light-emitting diode, characterised in that the method comprises a step of preparing a light-emitting layer (20) on a front face of a support (10), said emitting layer comprising at least two adjacent quantum wells (21, 22, 23) emitting at different wavelengths, said quantum wells (21, 22, 23) being in contact with the front face of the support. According to the invention, the step in which the light-emitting layer is deposited comprises a sub-step consisting in locally varying the temperature of a rear face of the support opposite the front face such that the front face of the support comprises at least two zones at different temperatures.

Abstract translation: 本发明涉及一种用于生产发光二极管的方法，其特征在于该方法包括在支撑体（10）的正面上准备发光层（20）的步骤，所述发射层包括在 以不同波长发射的至少两个相邻的量子阱（21,22,23），所述量子阱（21,22,23）与支撑体的前表面接触。 根据本发明，沉积发光层的步骤包括一个子步骤，其包括局部地改变与前表面相对的支撑件的后表面的温度，使得支撑体的前表面至少包括两个 不同温度下的区域。

公开(公告)号：EP2771912A4

公开(公告)日：2015-07-01

申请号：EP11874725

申请日：2011-10-28

Applicant: HEWLETT PACKARD DEVELOPMENT CO

Inventor： LIANG DI ,  BEAUSOLEIL RAYMOND G

IPC: H01L27/12 ,  G02B6/12 ,  G02F1/025 ,  H01L21/20

CPC classification number: H01L27/1203 ,  G02B6/122 ,  H01L21/02439 ,  H01L21/02444 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/8213 ,  H01L27/12

公开(公告)号：EP2504869A4

公开(公告)日：2014-11-26

申请号：EP10833736

申请日：2010-10-01

Applicant: TOSHIBA KK

Inventor： LESTER STEVEN ,  RAMER JEFF ,  WU JUN ,  ZHANG LING

IPC: H01L33/14 ,  H01L21/02 ,  H01L33/00 ,  H01L33/02 ,  H01L33/06 ,  H01L33/20 ,  H01L33/22 ,  H01L33/32

CPC classification number: H01L33/22 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658 ,  H01L33/0004 ,  H01L33/007 ,  H01L33/025 ,  H01L33/06 ,  H01L33/20 ,  H01L33/32

Abstract: A light emitting device and method for making the same is disclosed. The light-emitting device includes an active layer sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. The active layer emits lights when holes from the p-type semiconductor layer combine with electrons from the n-type semiconductor layer therein. The active layer includes a number of sub-layers and has a plurality of pits in which the side surfaces of a plurality of the sub-layers are in contact with the p-type semiconductor material such that holes from the p-type semiconductor material are injected into those sub-layers through the exposed side surfaces without passing through another sub-layer. The pits can be formed by utilizing dislocations in the n-type semiconductor layer and etching the active layer using an etching atmosphere in the same chamber used to deposit the semiconductor layers without removing the partially fabricated device.

Abstract translation: 公开了一种发光器件及其制造方法。 发光器件包括夹在p型半导体层和n型半导体层之间的有源层。 当来自p型半导体层的孔与其中的n型半导体层的电子结合时，有源层发光。 有源层包括多个子层，并且具有多个凹坑，其中多个子层的侧表面与p型半导体材料接触，使得来自p型半导体材料的孔为 通过暴露的侧表面注入到这些子层中，而不通过另一个子层。 可以通过利用n型半导体层中的位错并且使用在用于沉积半导体层的相同室中的蚀刻气氛来蚀刻有源层而不去除部分制造的器件来形成凹坑。

公开(公告)号：EP2498293A4

公开(公告)日：2014-11-19

申请号：EP10828333

申请日：2010-11-05

Applicant: NGK INSULATORS LTD

Inventor： MIYOSHI MAKOTO ,  SUMIYA SHIGEAKI ,  ICHIMURA MIKIYA ,  TANAKA MITSUHIRO

IPC: C23C16/02 ,  C23C16/30 ,  C23C16/34 ,  C30B25/02 ,  C30B29/38 ,  C30B29/40 ,  C30B29/68 ,  H01L21/02 ,  H01L21/205 ,  H01L21/338 ,  H01L29/10 ,  H01L29/20 ,  H01L29/47 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872

CPC classification number: H01L21/02381 ,  C23C16/0272 ,  C23C16/029 ,  C23C16/303 ,  C30B25/02 ,  C30B29/403 ,  C30B29/68 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/872

Abstract: Provided is an epitaxial substrate in which a silicon substrate is used as a base substrate, that allows a HEMT device with a high breakdown voltage to be achieved. An epitaxial substrate, in which a group of group-III nitride layers are formed on a (111) single crystal Si substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a surface of the substrate, includes: a first group-III nitride layer that is made of AlN and that is a layer with many defects configured of at least one kind from a columnar or granular crystal or domain; a second group-III nitride layer whose interface with the first group-III nitride layer is shaped into a three-dimensional concave-convex surface; a third group-III nitride layer that is epitaxially formed on the second group-III nitride layer; and the third group-III nitride layer that is a graded composition layer in which the proportion of existence of Al is smaller in a portion closer to a fourth group-III nitride.

公开(公告)号：EP1557870B1

公开(公告)日：2014-10-22

申请号：EP05000505.7

申请日：2005-01-12

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Hirota, Ryu Itami Works of ,  Nakahata, Seiji Itami Works of ,  Ueno, Masaki Itami Works of

IPC: H01L21/20 ,  C30B19/02 ,  C30B25/18 ,  C30B29/40 ,  C30B7/10 ,  C30B9/10 ,  H01L21/02

CPC classification number: C30B9/10 ,  C30B7/10 ,  C30B19/02 ,  C30B25/18 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02625

公开(公告)号：EP2565906A4

公开(公告)日：2013-12-04

申请号：EP11774747

申请日：2011-03-29

Applicant: NGK INSULATORS LTD

Inventor： MIYOSHI MAKOTO ,  SUMIYA SHIGEAKI ,  ICHIMURA MIKIYA ,  MAEHARA SOTA ,  TANAKA MITSUHIRO

IPC: H01L21/205 ,  C30B25/18 ,  C30B29/38 ,  C30B29/40 ,  H01L21/02 ,  H01L21/338 ,  H01L29/10 ,  H01L29/15 ,  H01L29/20 ,  H01L29/778 ,  H01L29/812 ,  H01L29/872

CPC classification number: H01L29/872 ,  C30B25/183 ,  C30B29/403 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L29/1075 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/7786

Abstract: Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. An epitaxial substrate in which a group of group-III nitride layers are formed on a base substrate made of (111)-oriented single crystal silicon such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate includes: a buffer layer including a composition modulation layer that is formed of a first composition layer made of AlN and a second composition layer made of Al x Ga 1-x N (0‰¤x x(n) is satisfied, where n represents the number of laminations of each of the first composition layer and the second composition layer (n is a natural number equal to or greater than two), and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side, to thereby cause a compressive strain to exist such that the compressive strain increases in a portion more distant from the base substrate.

公开(公告)号：EP1975984A3

公开(公告)日：2013-04-03

申请号：EP08153308.5

申请日：2008-03-26

Applicant: Fujitsu Ltd. ,  Hitachi Cable, Ltd.

Inventor： Imanishi, Kenji ,  Kikkawa, Toshihide ,  Tanaka, Takeshi ,  Moriya, Yoshihiko ,  Otoki, Yohei

IPC: H01L21/20 ,  H01L21/02

CPC classification number: H01L21/02581 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/0254 ,  H01L21/0262

Abstract: A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive.

公开(公告)号：EP2532022A2

公开(公告)日：2012-12-12

申请号：EP11739980.8

申请日：2011-01-28

Applicant: LG Siltron Inc.

Inventor： KIM, Yong Jin ,  LEE, Dong Kun ,  KIM, Doo Soo ,  LEE, Ho Jun ,  LEE, Kye Jin

IPC: H01L21/20

CPC classification number: H01L21/302 ,  C30B25/186 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/02664

Abstract: A method for manufacturing a gallium nitride (GaN) wafer is provided. In the method for manufacturing the GaN wafer according to an embodiment, an etch stop layer is formed on a substrate, and a first GaN layer is formed on the etch stop layer. A portion of the first GaN layer is etched with a silane gas, and a second GaN layer is formed on the etched first GaN layer. A third GaN layer is formed on the second GaN layer.