公开(公告)号：EP1427008A1

公开(公告)日：2004-06-09

申请号：EP03292810.3

申请日：2003-11-10

申请人： ALCATEL

发明人： Giraudet, Louis

IPC分类号： H01L21/60 ,  H01L21/603

CPC分类号： H01L24/12 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/1701 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/328 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2224/05169

摘要： Pour réduire la capacité d'un module électronique comprenant un composant actif (1) soudé sur une embase (2), et ainsi augmenter sa fréquence de coupure, le procédé consiste à prévoir sur le composant et sur l'embase plusieurs structure de plots (P1, P'1, P2, P3, P'3) et zones de contact (Z1, Z'1, Z2, Z3, Z'3). Des premières structures (P1, P'1, Z1, Z'1) sont adaptées pour être soudées par fusion d'un matériau de soudage. Des secondes structures (P2, Z2) de faibles surfaces sont conçues pour être soudées par thermocompression grâce à la force résultante d'attraction réciproque entre le composant et l'embase due à la fusion du matériau de soudage.
Application notamment pour la fabrication de composants optoélectroniques utilisés dans les systèmes de transmission optique à haut débit.

摘要翻译： 的电子模块的制造方法具有对安装在底座（2）上的活性成分（1）。 上部模块具有在上垫片（P2）的所有其通过焊料材料焊接到接触焊盘上的基区（Z2）与熔融温度在基区的上方一样。 在制造两个区域被推到一起并加热，以提供该组件。

公开(公告)号：EP2874315B1

公开(公告)日：2017-10-11

申请号：EP14193629.4

申请日：2014-11-18

申请人： Skyworks Solutions, Inc.

发明人： Roy, Ambarish ,  Zhu, Yu ,  Masse, Christophe

IPC分类号： H03K17/687 ,  H01L23/552 ,  H03K17/10

CPC分类号： H01L24/17 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/66 ,  H01L25/074 ,  H01L29/41758 ,  H01L29/66 ,  H01L2224/1701 ,  H01L2224/171 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/30105 ,  H01Q1/00 ,  H03K17/102 ,  H03K17/6871 ,  H01L2924/00

摘要： Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.

公开(公告)号：EP2923999A2

公开(公告)日：2015-09-30

申请号：EP15159573.3

申请日：2015-03-18

申请人： NXP B.V.

发明人： van Gemert, Leonardus ,  Tak, Coenraad ,  Oldsen, Marten ,  Bouman, Hendrik

IPC分类号： B81B7/00

CPC分类号： H01L24/17 ,  B81B7/0048 ,  B81B7/007 ,  H01L24/11 ,  H01L24/14 ,  H01L24/73 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/1401 ,  H01L2224/14134 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/26165 ,  H01L2224/26175 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/81855 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising:
fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and
fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

摘要翻译： 一个示例性实施例公开了一种具有芯片面积的芯片，其中芯片区域包括：突出区域; 刚性联接区域，具有位于所述伸出区域的一侧上的一组刚性联接点; 以及柔性联接区域，其具有一组柔性联接点，位于与刚性联接区域相对的伸出区域的一侧。 另一示例性实施例公开了一种用于制造管芯互连的方法，包括：在具有芯片面积的芯片内制造具有一组刚性耦合点的刚性耦合器区域; 限定所述芯片区域内的悬垂区域并与所述刚性耦合器区域相邻; 以及在与所述刚性联接器区域相对的所述伸出区域的一侧的所述芯片区域内制造具有一组柔性耦合点的柔性耦合器区域。

公开(公告)号：EP3319121A1

公开(公告)日：2018-05-09

申请号：EP17190243.0

申请日：2017-09-08

申请人： Nexperia B.V.

发明人： Chow, Wai Wong ,  Chau, On Lok

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/14 ,  H01L23/3114 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10145 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/1601 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

摘要： A leadless package semiconductor device has a top surface, a bottom surface opposite to the top surface, and multiple sidewalls between the top and bottom surfaces. At least one connection pad is disposed on the bottom surface. The connection pad includes a connection portion and at least one protrusion portion that extends from the connection portion and away from the bottom surface such that the protrusion portion and the connection portion surround a space on the bottom surface.

摘要翻译： 无引线封装半导体器件具有顶面，与顶面相对的底面以及顶面和底面之间的多个侧壁。 至少一个连接垫设置在底面上。 连接垫包括连接部分和从连接部分延伸并远离底表面的至少一个突出部分，使得突出部分和连接部分围绕底表面上的空间。

公开(公告)号：EP1427008B1

公开(公告)日：2008-04-23

申请号：EP03292810.3

申请日：2003-11-10

申请人： Alcatel Lucent

发明人： Giraudet, Louis

IPC分类号： H01L21/60 ,  H01L21/603

CPC分类号： H01L24/12 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/1701 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/328 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2224/05169

公开(公告)号：EP2923999A3

公开(公告)日：2016-01-13

申请号：EP15159573.3

申请日：2015-03-18

申请人： NXP B.V.

发明人： van Gemert, Leonardus ,  Tak, Coenraad ,  Oldsen, Marten ,  Bouman, Hendrik

IPC分类号： B81B7/00

CPC分类号： H01L24/17 ,  B81B7/0048 ,  B81B7/007 ,  H01L24/11 ,  H01L24/14 ,  H01L24/73 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/1401 ,  H01L2224/14134 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/26165 ,  H01L2224/26175 ,  H01L2224/29013 ,  H01L2224/29035 ,  H01L2224/32225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81801 ,  H01L2224/81855 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising:
fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and
fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.

公开(公告)号：EP2874315A1

公开(公告)日：2015-05-20

申请号：EP14193629.4

申请日：2014-11-18

申请人： Skyworks Solutions, Inc.

发明人： Roy, Ambarish ,  Zhu, Yu ,  Masse, Christophe

IPC分类号： H03K17/687 ,  H01L23/552 ,  H03K17/10

CPC分类号： H01L24/17 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/66 ,  H01L25/074 ,  H01L29/41758 ,  H01L29/66 ,  H01L2224/1701 ,  H01L2224/171 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/30105 ,  H01Q1/00 ,  H03K17/102 ,  H03K17/6871 ,  H01L2924/00

摘要： Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. Some implementations include a radio frequency switch arrangement having a ground plane, a stack and a first solder bump. The stack is arranged in relation to the ground plane, and includes switching elements coupled in series with one another, and a first end of the stack includes a respective terminal of a first one of the plurality of switching elements. The first solder bump is coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.

摘要翻译： 各种实现使得能够管理堆叠的集成电子设备的寄生电容和电压处理。 一些实现方式包括具有接地平面，堆叠和第一焊料凸块的射频开关装置。 堆叠相对于接地平面布置，并且包括彼此串联耦合的开关元件，并且堆叠的第一端包括多个开关元件中的第一个的相应端子。 第一焊料凸点耦合到多个开关元件中的第一个的相应端子，使得第一焊料凸块的至少一部分与多个开关元件中的一个或多个重叠，相对于 第一阈值，以便设置对射频开关装置的寄生电容的相应贡献。