公开(公告)号：EP1548825A3

公开(公告)日：2007-07-04

申请号：EP04029700.4

申请日：2004-12-15

申请人： SEIKO EPSON CORPORATION

发明人： Kori, Toshiaki

IPC分类号： H01L23/498

CPC分类号： H01L24/16 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： The invention relates to providing a semiconductor device in which a connecting terminal of a chip is prevented from being come off from a land of a circuit board. A semiconductor device includes a substrate 3 on which a plurality of first terminals 31 are formed and a chip 2 having a second terminal 21 electrically coupled to astride at least two first terminals 31 out of the plurality of the first terminals 31.

公开(公告)号：EP1548825A2

公开(公告)日：2005-06-29

申请号：EP04029700.4

申请日：2004-12-15

申请人： SEIKO EPSON CORPORATION

发明人： Kori, Toshiaki

IPC分类号： H01L23/498

CPC分类号： H01L24/16 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： The invention relates to providing a semiconductor device in which a connecting terminal of a chip is prevented from being come off from a land of a circuit board. A semiconductor device includes a substrate 3 on which a plurality of first terminals 31 are formed and a chip 2 having a second terminal 21 electrically coupled to astride at least two first terminals 31 out of the plurality of the first terminals 31.

摘要翻译： 本发明涉及提供一种半导体器件，其中防止了芯片的连接端子从电路板的焊盘脱落。 半导体器件包括其上形成有多个第一端子31的基板3和具有与多个第一端子31中的至少两个第一端子31跨接的第二端子21的芯片2。

公开(公告)号：EP2976784A1

公开(公告)日：2016-01-27

申请号：EP14718658.9

申请日：2014-03-21

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： MARION, François ,  BEDOIN, Alexis ,  BERGER, Frédéric ,  GUEUGNOT, Alain

IPC分类号： H01L23/00 ,  H01L31/02 ,  H01L21/56

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/1465 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1318 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13618 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13669 ,  H01L2224/16052 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/2741 ,  H01L2224/27618 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/83191 ,  H01L2224/83859 ,  H01L2224/83862 ,  H01L2224/83868 ,  H01L2224/83871 ,  H01L2224/83874 ,  H01L2224/83986 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2224/83 ,  H01L2924/01074 ,  H01L2224/27 ,  H01L2224/274 ,  H01L2224/276

摘要： This process for assembling first and second electronic components (50, 52) comprises: producing connecting elements on an assembly face of the first component (50) and producing connecting elements on an assembly face of the second component (52); depositing a liquid layer (70) of curable and electrically insulating material on the assembly face of the first and/or second component; arranging the first and second components (50, 52) one on the other so as to place the connecting elements of the second component facing the connecting elements of the first component; applying a force, in a preset direction (A), to the first and/or second components (50, 52) so as to create electrical interconnects each of which consists of one connecting element (56) of the first component (50) and one connecting element (58) of the second component (52); and curing the curable material (70). The connecting elements (56) of the first component (50) are hollow inserts having an open end and the connecting elements (58) of the second component (52) are solid elements (58) of lower hardness than that of the inserts (56), applying the force leads to the inserts (56) being inserted into the solid elements (58). The geometry of the inserts (56) and the geometry of the solid elements (58), and/or the relative position of the latter during the insertion, are chosen so as to leave a portion of the open end of the inserts (56) free during the insertion. The curable material (70) does not comprise deoxidising flux.

公开(公告)号：EP2668664A1

公开(公告)日：2013-12-04

申请号：EP12709304.5

申请日：2012-03-07

申请人： Siemens Aktiengesellschaft

发明人： HEDLER, Harry ,  SCHIEBER, Markus ,  WIRTH, Stefan ,  ZAPF, Jörg

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/10126 ,  H01L2224/11424 ,  H01L2224/13009 ,  H01L2224/13015 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/81801 ,  H01L2224/82101 ,  H01L2224/83 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01032 ,  H01L2924/01052 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/3436 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention relates to an integrated circuit (1), comprising a substrate (10) having a first surface (11) and an opposing second surface (12), wherein a functionalized region (13) is formed at least on the first surface (11) and wherein at least one electrical through-plating (40) is provided as a through-hole (42) which is continuously filled with an electrically conductive material (44) and which runs from the first surface (11) to the second surface (12) through the substrate (10). In order to ensure that the through-plating (40) can be reliably produced and is provided in a space-saving manner, the through-hole (42) has at least one gradation (46) on which a transition occurs from a smaller hole cross-section (d1) on the side of the first surface (11) to a larger hole cross-section (d2) on the side of the second surface (12).

摘要翻译： 集成电路的基板具有第一表面和相对的第二表面。 功能化区域至少形成在第一表面上。 提供至少一个电穿孔作为连续填充有导电材料并且从第一表面延伸穿过基底的第二表面的通孔。 为了确保能够可靠地制造贯通电镀并以节省空间的方式设置，通孔具有至少一个渐变，在第一表面侧的较小的空穴横截面发生转变， 在第二表面侧的较大的孔横截面。

公开(公告)号：EP2637202A3

公开(公告)日：2014-03-12

申请号：EP13164353.8

申请日：2008-09-26

申请人： Tessera, Inc.

发明人： Kwon, Jinsu

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3178 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/831 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/2064 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099

摘要： A packaged microelectronic assembly includes a microelectronic element (104) joined to a substrate (102, 402). The microelectronic element (104) has a front surface (122) and a plurality of first solid metal posts (110) extending away from the front surface (122). Each of the first posts (110) has a width (W2) in a direction of the front surface (122) and a height (H2) extending from the front surface (122), wherein the height (H2) is at least half of the width (W2). The substrate (102, 402) has a top surface (101, 401) and a plurality of second solid metal posts (108) extending from the top surface (101, 401) and joined to the first solid metal posts (110) by a fusible metal (130), each second post (108) having a second width (W1) in a direction along the top surface (101, 401) and each projecting to a second height (H1) above the top surface (101, 401). The substrate (402) also has conductive interconnects (407) extending through the substrate (402) and electrically connecting terminals at a bottom surface (403) opposite the top surface (401) with the second solid metal posts (108). The plurality of first solid metal posts (110) and the plurality of second solid metal posts (108) are etched metal posts. The posts (110, 108) may have a frustoconical shape defined by the etching process.

公开(公告)号：EP2287904A1

公开(公告)日：2011-02-23

申请号：EP10305877.2

申请日：2010-08-10

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： Marion, François

IPC分类号： H01L23/485 ,  H01L21/60 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/13005 ,  H01L2224/13011 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/13184 ,  H01L2224/13186 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13669 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/81099 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81201 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  Y10T29/49149 ,  Y10T29/49179 ,  Y10T29/49826 ,  H01L2924/01014 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/01051 ,  H01L2924/207

摘要： Ce procédé d'assemblage de deux composants électroniques (12, 16) par insertion d'inserts creux et ouverts (50) dans des éléments pleins convexes (14) de dureté inférieure à celle des inserts, consiste, lors de l'insertion d'un insert (50) dans un élément plein (14), à ce qu'au moins une surface (52) de l'extrémité ouverte (54) de l'insert (50) soit laissée libre de manière à créer un passage de sortie pour des gaz contenus dans l'insert (50).

摘要翻译： 该方法包括将开放和中空的插入件（50）插入凸形固体元件即焊接球（14）中，其中每个凸形实心元件的硬度低于每个插入件的硬度。 开口端即圆形开口（54）的表面或部分（52）从插入件移除，以便在将插入物插入凸形固体元件中时，为插入件中容纳的气体产生出口通道，其中长度 插入件的开口端大于凸形固体元件沿预定轴线的长度。

公开(公告)号：EP3319121A1

公开(公告)日：2018-05-09

申请号：EP17190243.0

申请日：2017-09-08

申请人： Nexperia B.V.

发明人： Chow, Wai Wong ,  Chau, On Lok

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/14 ,  H01L23/3114 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10145 ,  H01L2224/13011 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/1601 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/384 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

摘要： A leadless package semiconductor device has a top surface, a bottom surface opposite to the top surface, and multiple sidewalls between the top and bottom surfaces. At least one connection pad is disposed on the bottom surface. The connection pad includes a connection portion and at least one protrusion portion that extends from the connection portion and away from the bottom surface such that the protrusion portion and the connection portion surround a space on the bottom surface.

摘要翻译： 无引线封装半导体器件具有顶面，与顶面相对的底面以及顶面和底面之间的多个侧壁。 至少一个连接垫设置在底面上。 连接垫包括连接部分和从连接部分延伸并远离底表面的至少一个突出部分，使得突出部分和连接部分围绕底表面上的空间。

公开(公告)号：EP2637202A2

公开(公告)日：2013-09-11

申请号：EP13164353.8

申请日：2008-09-26

申请人： Tessera, Inc.

发明人： Kwon, Jinsu

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L24/14 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3178 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/831 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/2064 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099

摘要： A packaged microelectronic assembly includes a microelectronic element (104) joined to a substrate (102, 402). The microelectronic element (104) has a front surface (122) and a plurality of first solid metal posts (110) extending away from the front surface (122). Each of the first posts (110) has a width (W2) in a direction of the front surface (122) and a height (H2) extending from the front surface (122), wherein the height (H2) is at least half of the width (W2). The substrate (102, 402) has a top surface (101, 401) and a plurality of second solid metal posts (108) extending from the top surface (101, 401) and joined to the first solid metal posts (110) by a fusible metal (130), each second post (108) having a second width (W1) in a direction along the top surface (101, 401) and each projecting to a second height (H1) above the top surface (101, 401). The substrate (402) also has conductive interconnects (407) extending through the substrate (402) and electrically connecting terminals at a bottom surface (403) opposite the top surface (401) with the second solid metal posts (108). The plurality of first solid metal posts (110) and the plurality of second solid metal posts (108) are etched metal posts. The posts (110, 108) may have a frustoconical shape defined by the etching process.

摘要翻译： 一种封装的微电子组件包括一微电子元件（104）接合到衬底（102，402）。 所述微电子元件（104）具有前表面（122）和第一固体金属柱从所述前表面（122）延伸远离有多个（110）。 每个第一柱（110）的在所述前表面（122）和高度（H2）的方向上的宽度（W2）从所述前表面（122）worin的高度（H2）延伸的是至少一半 的宽度（W2）。 衬底（102，402）具有顶部表面（101，401）和第二固体金属柱从所述顶表面延伸的多个（108）（101，401），并通过一个连接到所述第一固体金属柱（110） 易熔金属（130），在沿着顶面（101，401）的方向上具有第二宽度（W1），每个第二柱（108），并且每个投射到顶部表面上方的第二高度（H1）（101，401） ， 如此的基板（402）具有导电互连（407）通过所述基板（402）和电连接端子在一个底表面（403）的顶面（401）相对地延伸与所述第二固体金属柱（108）。 第一固体金属柱（110）和第二固体金属柱（108）的分别设置于多个被蚀刻金属柱。 柱（110，108）可具有由蚀刻工艺所限定的截头圆锥形状。

公开(公告)号：EP2206145A4

公开(公告)日：2012-03-28

申请号：EP08835829

申请日：2008-09-26

申请人： TESSERA INC

发明人： KWON JINSU

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/14 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3178 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/1147 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2224/16 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81011 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/831 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/2064 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099

公开(公告)号：EP2735022A2

公开(公告)日：2014-05-28

申请号：EP12751154.1

申请日：2012-07-20

申请人： Qualcomm Incorporated

发明人： BAO, Zhongping ,  BURRELL, James D. ,  GU, Shiqun

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05558 ,  H01L2224/056 ,  H01L2224/1146 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/14142 ,  H01L2224/16057 ,  H01L2224/17051 ,  H01L2224/81211 ,  H01L2224/814 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Pillars having a directed compliance geometry are arranged to couple a semiconductor die to a substrate. The direction of maximum compliance of each pillar may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die and substrate. Pillars may be designed and constructed with various shapes having particular compliance characteristics and particular directions of maximum compliance. The shape and orientation of the pillars may be selected as a function of their location on a die to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning to increase surface of materials upon which the pillar is plated or deposited.

摘要翻译： 具有定向柔顺几何形状的柱被设置成将半导体管芯耦合到衬底。 每个柱的最大柔度方向可以与由半导体管芯和衬底的不等热膨胀和收缩引起的最大应力方向对齐。 支柱可以被设计和构造成具有特定顺应性特征和最大顺应性特定方向的各种形状。 柱的形状和取向可以根据它们在模具上的位置来选择，以适应在它们的位置处的应力的方向和大小。 一种方法包括通过图案化来制造具有特定形状的柱，以增加柱被镀敷或沉积在其上的材料的表面。