公开(公告)号：EP2711977B1

公开(公告)日：2018-06-13

申请号：EP12185004.4

申请日：2012-09-19

申请人： Atotech Deutschland GmbH

发明人： Beck, Thomas ,  Steinberger, Gerhard ,  Walter, Andreas

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/16507 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3841 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01042 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/05552

摘要： The present invention relates to a method for forming a copper pillar on a semiconducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

公开(公告)号：EP1665363A4

公开(公告)日：2006-11-15

申请号：EP04785094

申请日：2004-09-27

申请人： FLIP CHIP TECHNOLOGIES L L C

发明人： JOHNSON MICHAEL E ,  ELENIUS PETER ,  KIM DEOK HOON

IPC分类号： H01L21/66 ,  H01L20060101 ,  H01L21/44 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).

公开(公告)号：EP3306652A3

公开(公告)日：2018-04-25

申请号：EP17195798.8

申请日：2017-10-10

申请人： Sensors Unlimited, Inc.

发明人： PAIK, Namwoong ,  HUANG, Wei

IPC分类号： H01L21/60 ,  H01L23/485

CPC分类号： H01L27/14634 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14605 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/05571 ,  H01L2224/10145 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A method of forming bump structures (116) for interconnecting components includes dry etching a layer of insulating material (102) to create a pattern for bump structures. A seed layer (112) is deposited on the insulating material (102) over the pattern. The seed layer (112) is patterned with a photo resist material (114). The method also includes forming bump structures over the seed layer (112) and the photo resist material (114) with a plating material to form bump structures (116) in the pattern, wherein the bump structures are isolated from one another.

摘要翻译： 形成用于互连元件的凸块结构（116）的方法包括干法蚀刻绝缘材料层（102）以形成用于凸块结构的图案。 种子层（112）沉积在图案上的绝缘材料（102）上。 种子层（112）用光刻胶材料（114）构图。 该方法还包括利用电镀材料在籽晶层（112）和光致抗蚀剂材料（114）上形成凸块结构以在图案中形成凸块结构（116），其中凸块结构彼此隔离。

公开(公告)号：EP3273466A3

公开(公告)日：2018-04-11

申请号：EP17173147.4

申请日：2017-05-26

申请人： Renesas Electronics Corporation

发明人： YAJIMA, Akira ,  YAMADA, Yoshiaki

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/29 ,  H01L23/485 ,  H01L23/525

CPC分类号： H01L24/13 ,  H01L21/311 ,  H01L21/321 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13163 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13686 ,  H01L2224/1369 ,  H01L2224/16112 ,  H01L2224/16237 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/053

摘要： The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower surface; a conductive pillar formed on the upper surface of the conductor layer and having an upper surface, a lower surface, and a sidewall; a protection film covering the upper surface of the conductor layer and having an opening which exposes the upper surface and the sidewall of the conductive pillar; and a protection film covering the sidewall of the conductive pillar. Then, in plan view, the opening of the protection film is wider than the upper surface of the conductive pillar and exposes an entire region of an upper surface of the conductive pillar.

摘要翻译： 该半导体器件包括：半导体衬底; 导体层，形成在所述半导体基板上并具有上表面和下表面; 导电柱，形成在导体层的上表面上并具有上表面，下表面和侧壁; 覆盖导体层的上表面并具有暴露导电柱的上表面和侧壁的开口的保护膜; 以及覆盖导电柱侧壁的保护膜。 然后，在平面图中，保护膜的开口比导电柱的上表面宽，并且暴露出导电柱的上表面的整个区域。

公开(公告)号：EP1544916A1

公开(公告)日：2005-06-22

申请号：EP04029916.6

申请日：2004-12-16

申请人： Samsung Electronics Co., Ltd.

发明人： Song, Hoon ,  Shim, Dong-sik

IPC分类号： H01L23/485 ,  H01L29/06 ,  H01L21/60 ,  H05K3/34 ,  H01L23/13 ,  H05K1/11

CPC分类号： H01L24/13 ,  H01L23/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05578 ,  H01L2224/05599 ,  H01L2224/10145 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81365 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10157 ,  H01L2924/15151 ,  H01L2924/15787 ,  H01L2924/381 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/05552 ,  H01L2924/00

摘要： Aflip-chip package for implementing a fine solder ball, and a flip-chip packaging method using the same. The flip-chip package includes a first wafer (100) having a first electrode and a first under bump metal (111,112) (UBM) formed on the first electrode and electrically connected to the first electrode; and second wafer (200) opposing the first wafer and having a second electrode located in a position corresponding to the first electrode, and a second UBM (211,212) formed of the second electrode and electrically connected to the second electrode. The first wafer (100) has a depression formed on one or more areas adjacent to the first UBM (111,112), which depression partly receives a solder ball (133a,134a) that connects the first (111,112) and the second UBMs (211,212) upon flip-chip bonding of the first (100) and second (200) wafers. Since the UBM is formed as an embossing pattern, a fine solder ball can be implemented. Additionally, the reliability of the package can be improved.

摘要翻译： 用于实现精细焊球的微片芯片封装以及使用其的倒装芯片封装方法。 倒装芯片封装包括具有形成在第一电极上并电连接到第一电极的第一电极和第一下凸块金属（111,112）（UBM）的第一晶片（100） 和与第一晶片相对并且具有位于对应于第一电极的位置的第二电极的第二晶片（200）和由第二电极形成并电连接到第二电极的第二UBM（211,212）。 第一晶片（100）具有形成在与第一UBM（111,112）相邻的一个或多个区域上的凹陷，该凹陷部分地接收连接第一（111,112）和第二UBM（211,212）的焊球（133a，134a） 在第一（100）和第二（200）晶片的倒装芯片接合时。 由于UBM形成为压花图案，因此可以实现精细的焊球。 此外，可以提高包装的可靠性。

公开(公告)号：EP1531492A2

公开(公告)日：2005-05-18

申请号：EP04026606.6

申请日：2004-11-09

申请人： Stanley Electric Co., Ltd.

发明人： Tsuchiya, Masahiko ,  Horio, Naochika

IPC分类号： H01L23/492 ,  H01L21/56

CPC分类号： H01L24/81 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3157 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/02166 ,  H01L2224/0217 ,  H01L2224/02175 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/10135 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/10165 ,  H01L2224/10175 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12035 ,  H01L2924/19041 ,  H01L2924/3841 ,  H05K3/28 ,  H05K3/4007 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2224/9211 ,  H01L2224/81 ,  H01L2224/83

摘要： A confronting surface of a substrate (1) faces a first surface of a semiconductor element (30). Extension layers (4,5) are formed on the substrate at positions facing electrodes (36,37) on the semiconductor element (30). A levee film (14) is disposed on one of the confronting surface and the first surface. Openings (15,16) are formed through the levee film (14). Connection members (38,39) which is filled but is not completely filled in the openings (15,16) connect the electrodes (36,37) and the extension layers (4,5).

摘要翻译： 一衬底（1）的面对表面面对一个半导体元件（30）的第一表面上。 扩展层（4,5）在所述半导体元件（30）上的电极（36,37）对置的位置形成在基底上。 堤坝电影（14）设置在面对表面中的一个和所述第一表面。 开口（15,16）通过所述堤防电影（14）形成。 连接部件（38,39），所有这些被填充，但没有被完全填充呼叫在开口（15,16）连接的电极（36,37）和延伸层（4,5）。

公开(公告)号：EP1134805B1

公开(公告)日：2004-07-21

申请号：EP01110511.1

申请日：1996-03-18

申请人： Unitive International Limited

发明人： Mis, Joseph Daniel ,  Adema, Gretchen Maerker ,  Kellam, Mark D. ,  Rogers, W. Boyd

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/03 ,  H01L21/2885 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/13116 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method for fabricating solder bumps on a microelectronic device having contact pads includes the steps of depositing a titanium barrier layer on the device, forming an under bump metallurgy layer on the titanium barrier layer, and forming one or more solder bumps on the under bump metallurgy layer. The solder bump or bumps define exposed portions of the under bump metallurgy layer which are removed, and then the exposed portion of the titanium barrier layer is removed. The titanium barrier layer protects the underlying microelectronic device from the etchants used to remove the under bump metallurgy layer. The titanium layer also prevents the under bump metallurgy layer from forming a residue on the underlying microelectronic device. Accordingly, the titanium barrier layer allows the under bump metallurgy layer to be quickly removed without leaving residual matter thereby reducing the possibility of electrical shorts between solder bumps.

摘要翻译： 一种用于在具有接触垫的微电子器件上制造焊料凸块的方法包括以下步骤：在器件上沉积钛阻挡层;在钛阻挡层上形成凸块下金属化层;以及在凸块下金属化层上形成一个或多个焊料凸块 层。 一个或多个焊料凸块限定被去除的凸块下金属化层的暴露部分，然后去除钛阻挡层的暴露部分。 钛阻挡层保护下面的微电子器件免受用于去除凸块下冶金层的蚀刻剂的影响。 钛层还防止下凸块金属化层在下面的微电子器件上形成残留物。 因此，钛阻挡层可以快速去除凸块下冶金层而不会留下残余物质，从而降低了焊料凸块之间电短路的可能性。

公开(公告)号：EP0714123A2

公开(公告)日：1996-05-29

申请号：EP95303846.0

申请日：1995-06-06

申请人： SHARP KABUSHIKI KAISHA

发明人： Matsubara, Hiroshi

IPC分类号： H01L21/60

CPC分类号： H01L24/12 ,  H01L24/03 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/10122 ,  H01L2224/10145 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/75302 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/19041 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

摘要： A semiconductor device according to the present invention to be mounted on a mounting substrate includes: a connection electrode (22) formed on a surface of the semiconductor device; a solder bump (31) formed on the connection electrode the solder bump electrically and mechanically connecting the connection electrode (22) with a substrate electrode formed on the mounting substrate; and a solder drawing layer (23) provided on the surface of the semiconductor device in a periphery of the solder bump and having a surface portion (42b) composed of a solder-agreeable metal, the solder drawing layer retracting melted solder of the solder bump onto a surface of the solder drawing layer by contact with the melted solder.

公开(公告)号：EP0322121A1

公开(公告)日：1989-06-28

申请号：EP88311265.8

申请日：1988-11-28

申请人： BRITISH AEROSPACE PUBLIC LIMITED COMPANY

发明人： Hill, Peter Frederick

IPC分类号： H05K3/34 ,  H05K3/40

CPC分类号： H05K3/3442 ,  H01L2224/10145 ,  H05K1/0271 ,  H05K3/26 ,  H05K3/305 ,  H05K3/3494 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/10636 ,  H05K2201/10727 ,  H05K2201/10984 ,  H05K2201/2036 ,  H05K2203/087 ,  Y02P70/611 ,  Y02P70/613 ,  Y10S428/901 ,  Y10T156/1056 ,  Y10T156/1064 ,  Y10T428/24826 ,  Y10T428/24917

摘要： Flux residue drawn by capillary action into the small gap between a conductor pattern support e.g. a printed circuit board, and a leadless electronic component surface mounted on the support is hard to remove and may corrode the conductor pattern. Herein the component is fixed to the support by a pad of adhesive elastomer so as to give a larger and hence more easily cleanable gap between component and support and the component connector pads are coupled to the conductor pattern by way of solder pillars formed by pre-loading the component connector pads and the pattern with precisely defined amounts of solder and, e.g. during a vapour phase re-flow, causing the pre-loads to merge and form the solder pillars.

摘要翻译： 通过毛细管作用将导电残留物吸收到导体图案载体之间的小间隙中。 印刷电路板和安装在支撑体上的无引线电子部件表面难以去除并且可能腐蚀导体图案。 这里，组件通过粘合弹性体垫固定到支撑件上，以便在部件和支撑件之间产生较大的并因此更容易清洁的间隙，并且部件连接器焊盘通过由预制件形成的焊料柱连接到导体图案， 用精确定义的焊料量加载部件连接器焊盘和图案，例如 在气相再流动期间，使预加载合并并形成焊料柱。

公开(公告)号：EP3384530A1

公开(公告)日：2018-10-10

申请号：EP17707450.7

申请日：2017-02-10

申请人： Apple Inc.

发明人： HU, Hsin-Hua ,  PEDDER, James E. ,  BITA, Ion ,  CHOI, Jaein ,  TANG, Hairong ,  HSU, Chin Wei ,  CHALASANI, Sandeep ,  CHEN, Chih-Lei ,  ONO, Shinya ,  KANG, Sunggu ,  HUANG, Jung Yen ,  TSAI, Lun

IPC分类号： H01L25/075 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L25/0753 ,  H01L23/3157 ,  H01L23/3192 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/16 ,  H01L25/167 ,  H01L2224/10145 ,  H01L2224/11002 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16112 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11

摘要： Micro LED and microdriver chip integration schemes are described. In an embodiment a microdriver chip includes a plurality of trenches formed in a bottom surface of the microdriver chip, with each trench surrounding a conductive stud extending below a bottom surface of the microdriver chip body. Integration schemes are additionally described for providing electrical connection to conductive terminal contacts and micro LEDs bonded to a display substrate and adjacent to a microdriver chip.