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公开(公告)号：KR101814081B1
公开(公告)日：2018-01-03
申请号：KR1020100090173
申请日：2010-09-14
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/31 , H01L21/56 , H01L25/10 , H01L23/00 , H01L25/065
CPC分类号： H01L23/3128 , H01L21/565 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/19107 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： 집적회로패키지시스템의제조방법은, 버퍼층이부착되어있는몰드체이스를구비하는봉지시스템을제공하는단계와; 베이스기판을제공하는단계, 노출형상호연결부의 일부분상에버퍼층이부착되도록노출형상호연결부를상기베이스기판에연결하는단계, 베이스부품을베이스기판위에실장하는단계, 및봉지시스템으로상기베이스기판과노출형상호연결부위에베이스봉지재를형성하는단계를포함하는, 베이스집적회로패키지를형성하는단계와; 상기베이스봉지재로부터상기노출형상호연결부의일부분을노출시키되, 노출형상호연결부가제거되는버퍼층의특징을구비하도록봉지시스템을제거하는단계를포함한다.
摘要翻译： 一种制造集成电路封装系统的方法包括：提供密封系统，所述密封系统具有附接有缓冲层的模具槽; 提供基底，将暴露的互连连接到基底，以将缓冲层附着在暴露的互连的一部分上;将基底部件安装在基底上;以及用密封系统密封基底。 在暴露的互连上形成基础密封剂;形成基础集成电路封装; 去除封装系统以从基础封装剂暴露暴露的互连的一部分，其中封装系统具有从其去除暴露的互连的缓冲层的特征。
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公开(公告)号：KR101768659B1
公开(公告)日：2017-08-17
申请号：KR1020100092627
申请日：2010-09-20
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/31 , H01L23/498 , H01L21/56 , H01L25/03 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/00
CPC分类号： H01L23/49811 , H01L21/565 , H01L23/3128 , H01L23/49816 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/16 , H01L2224/32225 , H01L2224/45014 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06572 , H01L2225/06582 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： 본발명은, 기판을제공하는단계와, 기판상방에집적회로를장착하는단계와, 기판의상방에서기판에완충상호접속체를부착하는단계와, 기판의상방에완충상호접속체와집적회로를덮는봉입체를형성하는단계와, 봉입체내에완충상호접속체까지비아를형성하는단계를포함하는집적회로패키징시스템의제조방법에관한것이다.
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公开(公告)号：KR1020110030366A
公开(公告)日：2011-03-23
申请号：KR1020100090173
申请日：2010-09-14
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/31 , H01L21/56 , H01L25/10 , H01L23/00 , H01L25/065
CPC分类号： H01L23/3128 , H01L21/565 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/19107 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PURPOSE: An integrated circuit packaging system and a manufacturing method thereof are provided to offer simple and cost-effective encapsulation system by forming a buffer layer between a mold chase and a base integrated circuit package. CONSTITUTION: An encapsulation system(132) equipped with a mold chase(134) is provided. A base substrate(104) is arranged. An exposed interconnect unit(110) is connected to the base substrate so that a buffer layer is attached to a portion of the exposed interconnect unit. A base part(112) is mounted on the base substrate.
摘要翻译： 目的：提供一种集成电路封装系统及其制造方法，通过在模具追踪和基础集成电路封装之间形成缓冲层来提供简单且经济有效的封装系统。 构成：提供了一种装有模具追踪（134）的封装系统（132）。 设置基底（104）。 暴露的互连单元（110）连接到基底衬底，使得缓冲层附着到暴露的互连单元的一部分。 基部（112）安装在基底基板上。
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公开(公告)号：KR1020110068935A
公开(公告)日：2011-06-22
申请号：KR1020100128638
申请日：2010-12-15
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/498 , H01L21/48 , H01L21/56 , H01L21/683 , H01L25/10 , H01L25/00 , H01L23/00
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L23/49811 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68359 , H01L2221/68381 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PURPOSE: An integrated circuit package with a laminated interconnection unit and a manufacturing method thereof are provided to secure the alignment and position set of a conductive column with regard to a component pad by attaching a conductive column lead frame on a component side of a base package substrate. CONSTITUTION: A base package(102) comprises a component side(108) and a base package substrate(106). A component pad(112) is connected to a system pad(114) by an inner wiring(116). A system interconnection unit(118) is formed on the system pad. A base integrated circuit die(120) is connected to the component pad by a chip interconnection unit. A conductive column(126) is attached to the component pad or conductive adhesive(128).
摘要翻译： 目的：提供一种具有叠层互连单元的集成电路封装及其制造方法，用于通过将导电柱引线框架安装在基座封装的元件侧上来固定导电柱相对于元件焊盘的对准和位置组合 基质。 构成：基部封装（102）包括元件侧（108）和基底封装基板（106）。 组件衬垫（112）通过内部配线（116）连接到系统衬垫（114）。 在系统板上形成系统互连单元（118）。 基座集成电路管芯（120）通过芯片互连单元连接到元件焊盘。 导电柱（126）附接到部件焊盘或导电粘合剂（128）。
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公开(公告)号：KR1020110031891A
公开(公告)日：2011-03-29
申请号：KR1020100092627
申请日：2010-09-20
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/31 , H01L23/498 , H01L21/56 , H01L25/03 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/00
CPC分类号： H01L23/49811 , H01L21/565 , H01L23/3128 , H01L23/49816 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/16 , H01L2224/32225 , H01L2224/45014 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06541 , H01L2225/06572 , H01L2225/06582 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： PURPOSE: An integrated circuit packaging system with an encapsulated via and a method of manufacture thereof are provided to prevent damage in forming a via by supplying a physical barrier or a buffer unit. CONSTITUTION: In an integrated circuit packaging system with an encapsulated via and a method of manufacture thereof, a substrate is provided. An integrated circuit is mounted in the substrate. A shock-absorbing interconnect is attached to the substrate. A sealing member covering the shock-absorbing interconnect and the integrated circuit is formed on the substrate. A via is formed in the sealing member to the shock-absorbing interconnect. An interposer is installed in the sealing member.
摘要翻译： 目的：提供一种具有封装通孔及其制造方法的集成电路封装系统，以通过提供物理屏障或缓冲单元来防止形成通孔的损坏。 构成：在具有封装通孔的集成电路封装系统及其制造方法中，提供基板。 集成电路安装在基板中。 减震互连件附接到基板。 在基板上形成覆盖减震互连和集成电路的密封构件。 在密封构件中形成通孔以与减震互连。 插入件安装在密封件中。
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公开(公告)号：KR101805114B1
公开(公告)日：2017-12-05
申请号：KR1020110048661
申请日：2011-05-23
申请人： 스태츠 칩팩 피티이. 엘티디.
CPC分类号： H01L25/105 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/49517 , H01L23/49537 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45014 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2224/83385 , H01L2224/97 , H01L2225/0651 , H01L2225/06565 , H01L2225/06568 , H01L2225/1029 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： 집적회로패키징시스템의제조방법은, 제1 단자를형성하는단계; 집적회로를제1 단자에연결하는단계; 수직도전성포스트로제1 단자와집적회로위로연결되는제2 단자를형성하는단계로서수직도전성포스트는제1 단자또는제2 단자와일체로형성된단계; 및제1 단자와제2 단자의일부분들이노출된상태로집적회로와수직도전성포스트를감싸는단계를포함한다.
摘要翻译： 一种制造集成电路封装系统的方法，包括：形成第一端子; 将集成电路连接到第一终端; 形成连接至所述竖直导电底板1端子和所述集成电路的第二端子，其中所述竖直导电柱与所述第一端子或所述第二端子一体形成; 并且用第一和第二端子的一部分暴露的包装集成电路和垂直导电柱。
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公开(公告)号：KR1020110128748A
公开(公告)日：2011-11-30
申请号：KR1020110048661
申请日：2011-05-23
申请人： 스태츠 칩팩 피티이. 엘티디.
CPC分类号： H01L25/105 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/49517 , H01L23/49537 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45014 , H01L2224/45139 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2224/83385 , H01L2224/97 , H01L2225/0651 , H01L2225/06565 , H01L2225/06568 , H01L2225/1029 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L23/48 , H01L23/12 , H01L23/481 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： PURPOSE: An integrated circuit packaging system and a manufacturing method thereof are provided to improve reliability by mounting a second terminal on a first terminal. CONSTITUTION: A first terminal with a joint ring is formed. An integrated circuit(218) is connected to the first terminal. A second terminal(230), which is connected to the top parts of the first terminal and the integrated circuit by a vertical conductive post, is formed. The second terminal is connected to the top parts of the first terminal and the integrated circuit by the vertical conductive post which is surrounded by the joint ring. The vertical conductive post is integrally formed with the first terminal or the second terminal. The integrated circuit and the vertical conductive post are surrounded while a part of the second terminal and the first terminal is exposed.
摘要翻译： 目的：提供集成电路封装系统及其制造方法，以通过将第二端子安装在第一端子上来提高可靠性。 构成：形成具有接合环的第一端子。 集成电路（218）连接到第一端子。 形成通过垂直导电柱连接到第一端子的顶部和集成电路的第二端子（230）。 第二端子通过由接头环包围的垂直导电柱连接到第一端子和集成电路的顶部。 垂直导电柱与第一端子或第二端子一体形成。 集成电路和垂直导电柱被围绕，而第二端子和第一端子的一部分被暴露。
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公开(公告)号：KR101769995B1
公开(公告)日：2017-08-22
申请号：KR1020100038463
申请日：2010-04-26
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/31 , H01L23/29 , H01L23/552 , H01L25/065
CPC分类号： H01L23/3128 , H01L23/29 , H01L23/3135 , H01L23/552 , H01L25/0655 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/13091 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： 반도체장치는전도층을포함하는기판을가지고있다. 하나의상호연결된구조는기판위에서형성되고전기적으로전도층에연결되어있다. 반도체구성요소는기판위에실장된다. 인캡슐런트는반도체구성요소및 상호연결된구조위에증착된다. 하나의채널은상기상호연결된구조를노출시키기위해인캡슐런트내에형성된다. 솔더페이스트는상기차단막을형성하기전에채널내에증착된다. 차단막은상기인캡슐런트및 반도체다이상부에걸쳐상기채널로등각적으로도포될수 있다. 상기차단막은상기채널속으로연장되고전기적으로상기상호연결된구조에연결된다. 도킹핀은상기차단막위에형성되고그것은상기채널까지연장되고상기상호연결된구조에전기적으로연결된다. 모따기부는상기차단막의주변둘레에형성된다.
摘要翻译： 该半导体器件具有包括导电层的衬底。 一个互连结构形成在衬底上并且电连接到导电层。 半导体元件安装在基板上。 密封剂沉积在半导体元件和互连结构上。 一个通道形成在密封剂中以暴露互连结构。 在形成阻挡膜之前，焊膏沉积在通道中。 屏障可以共形地施加到密封剂和半导体管芯上方的通道。 阻挡层延伸到沟道中并电连接到互连结构。 对接销形成在阻挡膜上并延伸到通道并电连接到互连结构。 在阻挡膜的周围形成倒角。
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公开(公告)号：KR101741194B1
公开(公告)日：2017-05-30
申请号：KR1020100128638
申请日：2010-12-15
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/498 , H01L21/48 , H01L21/56 , H01L21/683 , H01L25/10 , H01L25/00 , H01L23/00
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L23/49811 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68359 , H01L2221/68381 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1052 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： 본발명은, 베이스패키지기판을제조하는단계; 리드프레임서포트를제공하는단계, 상호연결부고정구조형성단계를포함하는, 상기리드프레임서포트상에전도성소재를패터닝하는단계, 및상기베이스패키지기판에전도성소재를연결하는단계들에의해, 전도성칼럼리드프레임을베이스패키지기판에연결하는단계; 상기베이스패키지기판과전도성칼럼리드프레임사이에베이스패키지본체를형성하는단계; 및상기상호연결부고정구조를상기베이스패키지본체로부터노출시키기위해, 상기리드프레임서포트를상기전도성칼럼리드프레임에서제거하는단계;를포함하는집적회로패키지시스템제조방법을제공한다.
摘要翻译： 本发明提供了一种制造半导体器件的方法，包括：制造基础封装衬底; 提供引线框架支撑件，在引线框架支撑件上图案化导电材料，并且将导电材料互连到基底封装衬底，其中形成互连结构的步骤包括： 将框架连接到基础封装基板; 在基础封装衬底和导电柱引线框之间形成基础封装主体; 并且从导电柱引线框架移除引线框架支撑件以从基座封装主体暴露互连夹具结构。
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公开(公告)号：KR1020100119720A
公开(公告)日：2010-11-10
申请号：KR1020100038463
申请日：2010-04-26
申请人： 스태츠 칩팩 피티이. 엘티디.
IPC分类号： H01L23/31 , H01L23/29 , H01L23/552 , H01L25/065
CPC分类号： H01L23/3128 , H01L23/29 , H01L23/3135 , H01L23/552 , H01L25/0655 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/13091 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： PURPOSE: A semiconductor device and a method of forming shielding layer after encapsulation and grounded through interconnect structure are provided to prevent the generation of a void in encapsulant around a semiconductor die. CONSTITUTION: A substrate(52) includes a conductive layer. An interconnection structure is formed on a substrate and is electrically connected to the conductive layer. A semiconductor device is mounted in the substrate. An encapsulant is deposited on the semiconductor device and the interconnection structure.
摘要翻译： 目的：提供半导体器件和通过互连结构封装并接地之后形成屏蔽层的方法，以防止在半导体管芯周围的密封剂中产生空隙。 构成：衬底（52）包括导电层。 互连结构形成在基板上并与导电层电连接。 半导体器件安装在衬底中。 密封剂沉积在半导体器件和互连结构上。
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