公开(公告)号：US07724124B2

公开(公告)日：2010-05-25

申请号：US11704987

申请日：2007-02-12

Applicant: Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

Inventor： Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

IPC: H01C7/10

CPC classification number: H01C7/105 ,  B82Y30/00 ,  C03C14/006 ,  C03C2214/05 ,  C03C2214/08 ,  C03C2214/16 ,  C04B35/453 ,  C04B35/46 ,  C04B35/4682 ,  C04B35/47 ,  C04B35/565 ,  C04B35/624 ,  C04B35/62805 ,  C04B35/62807 ,  C04B35/62886 ,  C04B2235/3275 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/36 ,  C04B2235/405 ,  C04B2235/408 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/5454 ,  C04B2235/6025 ,  H01C7/12

Abstract: A low-capacitance multilayer chip varistor has capacitance lower than 0.5 pF at 1 MHz and has a characteristic of resisting more than thousands of times of 8 KV electrostatic shock, which comprises a ceramic main body, outer electrodes disposed at two ends of the ceramic main body and inner electrodes disposed therein; the ceramic main body comprises inorganic glass of 3˜50 wt % and semi-conductive or conductive particles of 50˜97 wt % with particle size of more than 0.1 μm, and a layer of inorganic glass film covers the surface of semi-conductive or conductive particles, wherein the inorganic glass film contains semi-conductive or conductive particles of submicron or nanometer which is smaller than 1 micron, and the quantity contained of semi-conductive or conductive particles is less than 20 wt % of that of inorganic glass.

Abstract translation: 低容量多层片式压敏电阻在1MHz时的电容低于0.5pF，具有耐8千伏静电电击的数千倍的特性，其中包括一陶瓷主体，外电极位于陶瓷主体的两端 主体和内部电极; 陶瓷主体包含3〜50重量％的无机玻璃和粒径大于0.1μm的50〜97重量％的半导电性或导电性粒子，无机玻璃膜层覆盖半导电性或 导电颗粒，其中无机玻璃膜含有小于1微米的亚微米或纳米的半导电或导电颗粒，并且半导体或导电颗粒所含的量小于无机玻璃的20重量％。

公开(公告)号：US20100117271A1

公开(公告)日：2010-05-13

申请号：US12458369

申请日：2009-07-09

Applicant: Ching-Hohn Lien ,  Jie-An Zhu ,  Cheng-Tsung Kuo ,  Jiu-Nan Lin ,  Zhi-Xian Xu ,  Hong-Zong Xu ,  Ting-Yi Fang ,  Xing-Xiang Huang

Inventor： Ching-Hohn Lien ,  Jie-An Zhu ,  Cheng-Tsung Kuo ,  Jiu-Nan Lin ,  Zhi-Xian Xu ,  Hong-Zong Xu ,  Ting-Yi Fang ,  Xing-Xiang Huang

IPC: B28B1/00

CPC classification number: H01C7/112 ,  C04B35/453 ,  C04B2235/32 ,  C04B2235/3203 ,  C04B2235/3215 ,  C04B2235/3217 ,  C04B2235/3224 ,  C04B2235/3227 ,  C04B2235/3229 ,  C04B2235/3232 ,  C04B2235/3236 ,  C04B2235/3239 ,  C04B2235/3241 ,  C04B2235/3244 ,  C04B2235/3251 ,  C04B2235/3258 ,  C04B2235/3262 ,  C04B2235/3267 ,  C04B2235/3272 ,  C04B2235/3275 ,  C04B2235/3279 ,  C04B2235/3281 ,  C04B2235/3284 ,  C04B2235/3286 ,  C04B2235/3291 ,  C04B2235/3293 ,  C04B2235/3294 ,  C04B2235/3298 ,  C04B2235/3409 ,  C04B2235/3418 ,  C04B2235/36 ,  C04B2235/44 ,  C04B2235/442 ,  C04B2235/95

Abstract: A process for producing zinc oxide varistors is to perform the doping of zinc oxide and the sintering of zinc oxide grains with a high-impedance sintering material through two independent procedures, so that the doped zinc oxide and the high-impedance sintering material are well mixed in a predetermined ratio and then used to make the zinc oxide varistors through conventional technology by low-temperature sintering (lower than 900° C.); the resultant zinc oxide varistors may use pure silver as inner electrode and particularly possess one or more of varistor properties, thermistor properties, capacitor properties, inductor properties, piezoelectricity and magnetism.

Abstract translation: 一种生产氧化锌压敏电阻的方法是通过两个独立的步骤，用高阻抗烧结材料进行氧化锌的掺杂和氧化锌晶粒的烧结，使掺杂的氧化锌和高阻抗烧结材料充分混合 以预定的比例，然后通过低温烧结（低于900℃）通过常规技术制造氧化锌变阻器; 所得到的氧化锌变阻器可以使用纯银作为内部电极，特别是具有变阻器特性，热敏电阻特性，电容器特性，电感特性，压电性和磁性中的一种或多种。

公开(公告)号：US20080286898A1

公开(公告)日：2008-11-20

申请号：US11798800

申请日：2007-05-17

Applicant: Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun Nan Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Wei-Cheng Lien

Inventor： Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun Nan Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Wei-Cheng Lien

IPC: H01L21/02 ,  H01B1/02

CPC classification number: H01C7/1006 ,  H01C7/108 ,  H01C7/112 ,  H01C7/115 ,  H01C7/18 ,  H01L27/0288 ,  H01L28/20 ,  Y10T428/2985 ,  Y10T428/2989 ,  Y10T428/2991

Abstract: A material composition having a core-shell microstructure suitable for manufacturing a varistor having outstanding electrical properties, the core-shell microstructure of the material composition at least comprising a cored-structure made of a conductive or semi-conductive material and a shelled-structure made from a glass material to wrap the cored-structure, and electrical properties of the varistors during low temperature of sintering process can be decided and designated by precisely controlling the size of the grain of the cored-structure and the thickness and insulation resistance of the insulating layer of the shelled-structure of material composition.

Abstract translation: 具有适于制造具有优异电性能的变阻器的核 - 壳微结构的材料组合物，所述材料组合物的芯 - 壳微结构至少包括由导电或半导电材料制成的芯结构和制成的壳形结构 从玻璃材料包裹芯结构，并且可以通过精确控制芯结构的晶粒尺寸和绝缘体的厚度和绝缘电阻来确定和指定压敏电阻在低温烧结过程中的电性能 层的材料组成的贝壳结构。

公开(公告)号：US20080191834A1

公开(公告)日：2008-08-14

申请号：US11704987

申请日：2007-02-12

Applicant: Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

Inventor： Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Xing-Guang Huang ,  Wei-Cheng Lien

IPC: H01C7/12 ,  C03C11/00

CPC classification number: H01C7/105 ,  B82Y30/00 ,  C03C14/006 ,  C03C2214/05 ,  C03C2214/08 ,  C03C2214/16 ,  C04B35/453 ,  C04B35/46 ,  C04B35/4682 ,  C04B35/47 ,  C04B35/565 ,  C04B35/624 ,  C04B35/62805 ,  C04B35/62807 ,  C04B35/62886 ,  C04B2235/3275 ,  C04B2235/3284 ,  C04B2235/3298 ,  C04B2235/36 ,  C04B2235/405 ,  C04B2235/408 ,  C04B2235/5436 ,  C04B2235/5445 ,  C04B2235/5454 ,  C04B2235/6025 ,  H01C7/12

Abstract: A low-capacitance multilayer chip varistor has capacitance lower than 0.5 pF at 1 MHz and has a characteristic of resisting more than thousands of times of 8 KV electrostatic shock, which comprises a ceramic main body, outer electrodes disposed at two ends of the ceramic main body and inner electrodes disposed therein; the ceramic main body comprises inorganic glass of 3˜50 wt % and semi-conductive or conductive particles of 50˜97 wt % with particle size of more than 0.1 μm, and a layer of inorganic glass film covers the surface of semi-conductive or conductive particles, wherein the inorganic glass film contains semi-conductive or conductive particles of submicron or nanometer which is smaller than 1 micron, and the quantity contained of semi-conductive or conductive particles is less than 20 wt % of that of inorganic glass.

Abstract translation: 低容量多层片式压敏电阻在1MHz时的电容低于0.5pF，具有耐8千伏静电电击的数千倍的特性，其中包括一陶瓷主体，外电极位于陶瓷主体的两端 主体和内部电极; 陶瓷主体包括3〜50重量％的无机玻璃和50〜97重量％的粒径大于0.1微米的半导体或导电颗粒，无机玻璃膜层覆盖半导体或 导电颗粒，其中无机玻璃膜含有小于1微米的亚微米或纳米的半导电或导电颗粒，并且半导体或导电颗粒所含的量小于无机玻璃的20重量％。

公开(公告)号：US20070273469A1

公开(公告)日：2007-11-29

申请号：US11440064

申请日：2006-05-25

Applicant: Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

Inventor： Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

IPC: H01C7/10

CPC classification number: H01C7/10 ,  H01C7/112 ,  H01C7/18

Abstract: A multilayer zinc oxide varistor without bismuth oxide system ingredients, and having variable breakdown voltages by controlling the thickness of the ceramic material; the varistor is bismuth-free and composed of zinc oxide as the primary constituent with alkaline earth element (Ba) as first additive, at least one of transition elements of Mn, Co, Cr, or Ni as second additives, at least one of rare earth elements of Pr, La, Ce, Nd or Tb as third additives and at least one of B, Si, Se, Al, Ti, W, Sn, Sb, Na, or K as rest additives, and the bismuth-free and zinc oxide based varistor exhibits an excellent ESD (Electro-Static Discharge) withstanding characteristic.

Abstract translation: 一种不含氧化铋体系成分的多层氧化锌压敏电阻，通过控制陶瓷材料的厚度具有可变的击穿电压; 所述变阻器是无铋的，以氧化锌为主要成分的碱土金属元素（Ba）作为第一添加剂，Mn，Co，Cr或Ni的过渡元素中的至少一种作为第二添加剂，至少一种稀有金属 作为第三添加剂的Pr，La，Ce，Nd或Tb的土元素，作为剩余添加剂的B，Si，Se，Al，Ti，W，Sn，Sb，Na或K中的至少一种， 基于氧化锌的变阻器具有优异的ESD（静电放电）耐受特性。

公开(公告)号：US08263432B2

公开(公告)日：2012-09-11

申请号：US11798800

申请日：2007-05-17

Applicant: Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nan Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Wei-Cheng Lien

Inventor： Ching-Hohn Lien ,  Cheng-Tsung Kuo ,  Jun-Nan Lin ,  Jie-An Zhu ,  Li-Yun Zhang ,  Wei-Cheng Lien

IPC: H01L21/02

CPC classification number: H01C7/1006 ,  H01C7/108 ,  H01C7/112 ,  H01C7/115 ,  H01C7/18 ,  H01L27/0288 ,  H01L28/20 ,  Y10T428/2985 ,  Y10T428/2989 ,  Y10T428/2991

Abstract: A material composition having a core-shell microstructure suitable for manufacturing a varistor having outstanding electrical properties, the core-shell microstructure of the material composition at least comprising a cored-structure made of a conductive or semi-conductive material and a shelled-structure made from a glass material to wrap the cored-structure, and electrical properties of the varistors during low temperature of sintering process can be decided and designated by precisely controlling the size of the grain of the cored-structure and the thickness and insulation resistance of the insulating layer of the shelled-structure of material composition.

Abstract translation: 具有适于制造具有优异电性能的变阻器的核 - 壳微结构的材料组合物，所述材料组合物的芯 - 壳微结构至少包括由导电或半导电材料制成的芯结构和制成的壳形结构 从玻璃材料包裹芯结构，并且可以通过精确控制芯结构的晶粒尺寸和绝缘体的厚度和绝缘电阻来确定和指定压敏电阻在低温烧结过程中的电性能 层的材料组成的贝壳结构。

公开(公告)号：US07541910B2

公开(公告)日：2009-06-02

申请号：US11440064

申请日：2006-05-25

Applicant: Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

Inventor： Wei-Cheng Lien ,  Cheng-Tsung Kuo ,  Jun-Nun Lin ,  Jie-An Zhu ,  Li-Yun Zhang

IPC: H01C7/10

CPC classification number: H01C7/10 ,  H01C7/112 ,  H01C7/18

Abstract: A multilayer zinc oxide varistor without bismuth oxide system ingredients, and having variable breakdown voltages by controlling the thickness of the ceramic material; the varistor is bismuth-free and composed of zinc oxide as the primary constituent with alkaline earth element (Ba) as first additive, at least one of transition elements of Mn, Co, Cr, or Ni as second additives, at least one of rare earth elements of Pr, La, Ce, Nd or Tb as third additives and at least one of B, Si, Se, Al, Ti, W, Sn, Sb, Na, or K as rest additives, and the bismuth-free and zinc oxide based varistor exhibits an excellent ESD (Electro-Static Discharge) withstanding characteristic.

Abstract translation: 一种不含氧化铋体系成分的多层氧化锌压敏电阻，通过控制陶瓷材料的厚度具有可变的击穿电压; 所述变阻器是无铋的，以氧化锌为主要成分的碱土金属元素（Ba）作为第一添加剂，Mn，Co，Cr或Ni的过渡元素中的至少一种作为第二添加剂，至少一种稀有金属 作为第三添加剂的Pr，La，Ce，Nd或Tb的土元素，作为剩余添加剂的B，Si，Se，Al，Ti，W，Sn，Sb，Na或K中的至少一种， 基于氧化锌的变阻器具有优异的ESD（静电放电）耐受特性。