公开(公告)号：US10924089B1

公开(公告)日：2021-02-16

申请号：US17010890

申请日：2020-09-03

Applicant: Faraday Technology Corporation ,  FARADAY TECHNOLOGY CORPORATION

Inventor： Xiao-Dong Fei ,  Wei Wang ,  San-Yueh Huang

IPC: H03K3/0233

Abstract: A comparing circuit and a comparing module with hysteresis are provided. The comparing module includes a first resistor, a second resistor, and the comparing circuit, which are electrically connected to each other. A comparison voltage is determined according to an input voltage and the resistances of the first resistor and the second resistor. The comparing circuit includes an input circuit, an eternal circuit, and a coupling module. The coupling module includes a first coupling transistor, a second coupling transistor, a third transistor, and a fourth coupling resistor. Control terminals of the first coupling transistor and the second coupling transistor are selectively electrically connected to either one of a first terminal and a second terminal. The second terminals of the third coupling transistor and the fourth coupling transistor are selectively electrically connected to either one of the first terminal and the second terminal.

公开(公告)号：US09432046B1

公开(公告)日：2016-08-30

申请号：US14855778

申请日：2015-09-16

Applicant: FARADAY TECHNOLOGY CORPORATION ,  FARADAY TECHNOLOGY CORPORATION

Inventor： Guang-Wen Yu ,  Xing-Bo Ding ,  Min-Yuan Wu

IPC: H03M1/34 ,  H03M1/44 ,  H03M1/12

CPC classification number: H03M1/468 ,  H03M1/1245 ,  H03M1/38 ,  H03M1/403

Abstract: A successive approximation analog-to-digital converter includes a first capacitance bank, a second capacitance bank, a bridge capacitor, a switch set, a comparator and a successive approximation register logic circuit. The first capacitance bank is connected with a first node. The second capacitance bank is connected with a second node. The bridge capacitor is connected between the first node and the second node. Two first input terminals of the comparator are connected with the first node and the intermediate level, respectively. An output terminal of the comparator generates a comparing signal. The successive approximation register logic circuit receives the comparing signal, and generates the switching signal and a digital data signal. The switch set selectively provides one of a low reference level, a high reference level, an input level and an intermediate level to the first capacitance bank and the second capacitance bank.

Abstract translation: 逐次逼近模数转换器包括第一电容组，第二电容组，桥式电容器，开关组，比较器和逐次逼近寄存器逻辑电路。 第一电容组与第一节点连接。 第二电容组与第二节点连接。 桥式电容器连接在第一节点和第二节点之间。 比较器的两个第一输入端分别与第一节点和中间电平连接。 比较器的输出端产生比较信号。 逐次逼近寄存器逻辑电路接收比较信号，并产生切换信号和数字数据信号。 开关组选择性地将第一电容组和第二电容组提供低参考电平，高参考电平，输入电平和中间电平中的一个。

公开(公告)号：US09276596B1

公开(公告)日：2016-03-01

申请号：US14726625

申请日：2015-06-01

Applicant: FARADAY TECHNOLOGY CORPORATION ,  FARADAY TECHNOLOGY CORPORATION

Inventor： Xingbo Ding ,  Feng Xu ,  Min-Yuan Wu

IPC: H03M1/12 ,  H03M1/00 ,  H03M1/42 ,  H03M1/06

CPC classification number: H03M1/002 ,  H03M1/1295 ,  H03M1/468

Abstract: An analog to digital converting apparatus and an initial method thereof are provided. The analog to digital converting apparatus includes a first and a second switching capacitor units, a circuit unit, a first and a second initialization switches, a third and a fourth capacitors and a logic buffer. The first and the second switching capacitor units respectively couple first capacitors and second capacitors to a first logic voltage, a second logic voltage or a first or a second input voltage according to a first control signal, and respectively generate a first and a second voltage. The circuit unit compares the first voltage and the second voltage to generate the first control signal. The first and the second initialization switches are respectively connected in series between the first and the second voltage and a common-mode endpoint. The logic buffer outputs the first or the second logic voltage to the common-mode endpoint.

Abstract translation: 提供了一种模数转换装置及其初始方法。 模数转换装置包括第一和第二开关电容器单元，电路单元，第一和第二初始化开关，第三和第四电容器和逻辑缓冲器。 第一和第二开关电容器单元根据第一控制信号分别将第一电容器和第二电容器耦合到第一逻辑电压，第二逻辑电压或第一或第二输入电压，并分别产生第一和第二电压。 电路单元比较第一电压和第二电压以产生第一控制信号。 第一和第二初始化开关分别串联连接在第一和第二电压和共模端点之间。 逻辑缓冲器将第一或第二逻辑电压输出到共模端点。

公开(公告)号：US10811899B2

公开(公告)日：2020-10-20

申请号：US16435917

申请日：2019-06-10

Applicant: Faraday Technology Corporation ,  FARADAY TECHNOLOGY CORPORATION

Inventor： Xiao-Dong Fei ,  Zheng-Xiang Wang ,  Song-Rong Han ,  Wei Wang

IPC: H02J9/06 ,  G05F1/59 ,  G06F1/26

Abstract: A power switching circuit receives a first power, a second power and a switching signal, and generates an output power. The power switching circuit includes a first power path and a second power path. The first power path is connected with the first power. The second power path is connected with the second power. When the switching signal in a logic high level, the first power path is in a conducting state and the second power path is in a non-conducting state. Consequently, the first power is selected as the output power by the power switching circuit. When the switching signal in a logic low level, the first power path is in the non-conducting state and the second power path is in the conducting state. Consequently, the second power is selected as the output power by the power switching circuit.

公开(公告)号：US20230093425A1

公开(公告)日：2023-03-23

申请号：US17510974

申请日：2021-10-26

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yi-Shan LI ,  Chi-Mao CHEN ,  Duc Anh NGUYEN ,  Po-Chen LO ,  Shung-Ru LIN

IPC: H01L23/528

Abstract: A power mesh structure for an integrated circuit is provided. A power switch cell is installed on the chip of the integrated circuit to control the switching operations of the power domain. The power meshes of the power mesh structure is specially designed. The power wires with different electrical properties are arranged in the same column or the same row to reduce the layout area of the power mesh on the material layer.

公开(公告)号：US11515862B2

公开(公告)日：2022-11-29

申请号：US17722669

申请日：2022-04-18

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yu-Hao Liu ,  Sheng-Hua Chen ,  Cheng-Hsing Chien

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037

Abstract: A true single-phase clock (TSPC) D flip-flop includes four stages. The four stages are serially connected between the input terminal and the output terminal of the TSPC D-type flip-flop. Each stage is selectively equipped with two connecting devices. One of the two connecting devices is a resistive element. The other of the two connecting devices is a short circuit element. When the node between two stages is in the floating state, the voltage change is slowed down by the resistive element. Consequently, the possibility of causing the function failure of the D-type flip-flop is minimized.

公开(公告)号：US11418207B1

公开(公告)日：2022-08-16

申请号：US17355173

申请日：2021-06-23

Applicant: Artery Technology Co., Ltd. ,  FARADAY TECHNOLOGY CORPORATION

Inventor： Zhengxiang Wang ,  Feng Xu ,  Wei-Tai Tsai ,  Chiao-Wen Lo

IPC: H03M1/12 ,  H03M1/46

Abstract: An analog-to-digital converter (ADC) device equipped with a conversion suspension function and an associated operation method thereof are provided. The ADC device includes: an interleaved clock controller, arranged to generate a first clock signal and a second clock signal according to a master clock signal; and a multi-ADC circuit, coupled to the interleaved clock controller, arranged to perform analog-to-digital conversion. The multi-ADC circuit includes a first ADC and a second ADC, wherein the first ADC performs sampling and conversion operations according to the first clock signal, and the second ADC performs sampling and conversion operations according to the second clock signal. Based on the timing control of the first clock signal and the second clock signal, when any ADC of the first ADC and the second ADC is performing a sampling operation, the other ADC of the first ADC and the second ADC suspends conversion.

公开(公告)号：US20210313970A1

公开(公告)日：2021-10-07

申请号：US17178194

申请日：2021-02-17

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： LING CHEN ,  Andrew Chao ,  XIAO-DONG FEI

IPC: H03K3/012 ,  H03K5/01 ,  H03K5/1252 ,  H03K3/037 ,  H04B1/16

Abstract: An apparatus for performing baseline wander correction (BLWC) with the aid of differential wander current sensing includes filters and a correction circuit. The filters are positioned in a front-end circuit of a receiver and coupled to a set of input terminals of the receiver, and filter a set of input signals on the set of input terminals to generate a set of differential signals on a set of secondary terminals, for further usage by the receiver. The correction circuit is positioned in the frontend circuit and electrically connected to the set of input terminals and the set of secondary terminals, and performs BLWC on the set of differential signals according to the set of input signals. In the correction circuit, amplifiers and resistors form a differential wander current sensor to sense differential wander current, and a set of current mirrors generate corresponding baseline wander compensation current to perform BLWC.

公开(公告)号：US20170279644A1

公开(公告)日：2017-09-28

申请号：US15241618

申请日：2016-08-19

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Yuan-Min Hu ,  Jhen-Yu Hou

IPC: H04L27/00

CPC classification number: H04L27/0014 ,  H03K3/00 ,  H03K5/1252 ,  H03L7/00 ,  H03L7/08 ,  H04J3/04 ,  H04L2027/0036

Abstract: A RXLOS deglitch apparatus for a receiver is provided. The RXLOS deglitch apparatus includes a sampler, an edge detecting unit and a finite state machine. The sampler receives a recovered clock, and samples a RXLOS signal according to the recovered clock. Consequently, a sampled RXLOS signal is generated. The edge detecting unit receives the RXLOS signal. When a logic level of the RXLOS signal is changed, an edge detection signal is activated by the edge detecting unit. The finite state machine receives the edge detection signal and the sampled RXLOS signal, generates an edge rest signal to control the edge detecting unit, and outputs a filtered RXLOS signal.

公开(公告)号：US11726944B2

公开(公告)日：2023-08-15

申请号：US17542531

申请日：2021-12-06

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Bu-Qing Ping

IPC: G06F13/34 ,  G06F13/42 ,  H04L69/324

CPC classification number: G06F13/4221 ,  H04L69/324 ,  G06F2213/0026

Abstract: The invention provides a transaction layer circuit of a PCIe. The transaction layer circuit includes transaction layer processing channels, a channel selection circuit, and a merge circuit. The transaction layer processing channels are coupled to a data bus transmitting at least one packet data output by a data link layer circuit of the PCIe. The channel selection circuit receives packet start/end location information in a current clock cycle from the data link layer circuit, and distributes at least one packet data in the current clock cycle to at least one transaction layer processing channel according to the packet start/end location information. The merge circuit is coupled to the transaction layer processing channels and selectively merges transaction layer processing results output by the transaction layer processing channels based on the distribution of the packet data in the current clock cycle to the transaction layer processing channels via the channel selection circuit.