公开(公告)号：US07385451B2

公开(公告)日：2008-06-10

申请号：US10537634

申请日：2003-11-27

申请人： Hugues Beaulaton ,  Philippe Gorisse ,  Nadim Khlat

发明人： Hugues Beaulaton ,  Philippe Gorisse ,  Nadim Khlat

IPC分类号： H03L7/00

CPC分类号： H03M7/3022 ,  H03L7/1976

摘要： A noise shaping arrangement for a phase locked loop includes a first order sigma-delta modulator arranged to provide a first-order quantized output and a feedback path output. A second order sigma-delta modulator is arranged to receive the feedback path output and provides a second order quantized output. A combination block combines the first and second order quantized outputs to provide a combined third order quantized output, which provides noise shaping with a frequency notch spectrum. In this way a new quantization noise shape of third order is provided, such that quantization phase noise may be lowered, the PLL loop bandwidth may be increased, modulation phase error may be reduced and PLL locking speed increased.

摘要翻译： 用于锁相环的噪声整形装置包括布置成提供一阶量化输出和反馈路径输出的一阶Σ-Δ调制器。 第二级Σ-Δ调制器被布置成接收反馈路径输出并提供二阶量化输出。 组合块组合了第一和第二阶量化输出以提供组合的三阶量化输出，其提供具有频率陷波频谱的噪声整形。 以这种方式，提供三阶新的量化噪声形状，使得量化相位噪声可能降低，PLL环路带宽可能增加，调制相位误差可能降低，PLL锁定速度提高。

公开(公告)号：US08598945B2

公开(公告)日：2013-12-03

申请号：US13116386

申请日：2011-05-26

申请人： Philippe Gorisse

发明人： Philippe Gorisse

IPC分类号： G05F1/575 ,  H02M3/07 ,  H03L7/24

CPC分类号： H02M3/07

摘要： A high voltage charge-pump includes a plurality of voltage boosting stages, a low voltage input, and at least one clock input. A sensing charge-pump having a voltage detector output has at least one voltage sensing stage that is communicably coupled to at least one of the plurality of voltage boosting stages. A loop filter in a feedback control loop includes a voltage detector input coupled to the voltage detector output, a voltage reference input, and a voltage error output. A voltage controlled oscillator (VCO) with a variable frequency output has a voltage error input coupled to the voltage error output. The feedback control loop also includes at least one driver having a variable frequency input coupled to the variable frequency output and at least one clock output coupled to the at least one clock input.

摘要翻译： 高压电荷泵包括多个升压级，低电压输入和至少一个时钟输入。 具有电压检测器输出的感测电荷泵具有至少一个电压感测级，其可通信地耦合到多个升压级中的至少一个。 反馈控制回路中的环路滤波器包括耦合到电压检测器输出的电压检测器输入，电压参考输入和电压误差输出。 具有可变频率输出的压控振荡器（VCO）具有耦合到电压误差输出的电压误差输入。 反馈控制回路还包括至少一个驱动器，其具有耦合到可变频率输出的可变频率输入和耦合到至少一个时钟输入的至少一个时钟输出。

公开(公告)号：US07880516B2

公开(公告)日：2011-02-01

申请号：US11910062

申请日：2005-03-31

申请人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

发明人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/081 ,  H03L7/1976

摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.

摘要翻译： 一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号和分频信号之间的差。 一种包含锁相环的装置。 锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

公开(公告)号：US20080265958A1

公开(公告)日：2008-10-30

申请号：US11910062

申请日：2005-03-31

申请人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

发明人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/081 ,  H03L7/1976

摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.

摘要翻译： 一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号与分频信号之间的差。 一种包含锁相环的装置。 锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

公开(公告)号：US08401500B1

公开(公告)日：2013-03-19

申请号：US12706544

申请日：2010-02-16

申请人： Ruediger Bauder ,  Nadim Khlat ,  Edward T. Spears ,  Jean-Frederic Chiron ,  Philippe Gorisse

发明人： Ruediger Bauder ,  Nadim Khlat ,  Edward T. Spears ,  Jean-Frederic Chiron ,  Philippe Gorisse

IPC分类号： H01Q11/12 ,  H04K3/00

CPC分类号： G06F1/26 ,  H04K3/00 ,  H04K2203/30

摘要： The present disclosure relates to an RF power amplifier (PA) power supply that includes a series pass circuit coupled across a direct current (DC)-to-DC converter to receive a power supply input signal, such as provided from a battery, to provide a power supply output signal to at least a first RF PA based on an output setpoint. Control circuitry selects between a switching supply operating mode and a non-switching supply operating mode based on the output setpoint. During the switching supply operating mode, the DC-to-DC converter provides the power supply output signal and during the non-switching supply operating mode, the series pass circuit provides the power supply output signal.

摘要翻译： 本公开涉及一种RF功率放大器（PA）电源，其包括跨直流（DC）至DC转换器耦合的串联传递电路，以接收诸如由电池提供的电源输入信号，以提供 基于输出设定点至少至少第一RF PA的电源输出信号。 控制电路根据输出设定值在开关电源工作模式和非开关电源工作模式之间进行选择。 在开关电源工作模式期间，DC-DC转换器提供电源输出信号，在非开关电源工作模式期间，串联电路提供电源输出信号。

公开(公告)号：US20120313701A1

公开(公告)日：2012-12-13

申请号：US13316229

申请日：2011-12-09

申请人： Nadim Khlat ,  Michael R. Kay ,  Philippe Gorisse

发明人： Nadim Khlat ,  Michael R. Kay ,  Philippe Gorisse

IPC分类号： H03G1/00

CPC分类号： H03F1/025 ,  H02M3/07 ,  H03F1/0244 ,  H03F1/0277 ,  H03F1/42 ,  H03F3/195 ,  H03F3/245 ,  H03F3/3022 ,  H03F3/45475 ,  H03F3/505 ,  H03F3/72 ,  H03F2200/102 ,  H03F2200/204 ,  H03F2200/36 ,  H03F2200/375 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2200/78 ,  H03F2203/45526 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45694 ,  H03F2203/45712 ,  H03F2203/45718 ,  H03F2203/7221

摘要： Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system including a parallel amplifier and a switch mode power supply converter cooperatively coupled to generate a power supply voltage at a power supply output coupled to a linear RF power amplifier. The parallel amplifier output is in communication with the power amplifier supply output. The parallel amplifier governs operation of the switch mode power supply converter and regulates the power amplifier supply voltage base on a VRAMP signal. The parallel amplifier circuit includes an open loop high frequency compensation assist circuit that generates a high frequency ripple compensation current based on an estimate of the high frequency ripple currents contained in a ripple current of the power inductor. The high frequency ripple compensation current is injected into the parallel amplifier circuit output to cancel out high frequency ripple currents at the power amplifier supply output.

摘要翻译： 在详细描述中公开的实施例涉及一种伪包络跟随器功率管理系统，其包括协同耦合以在耦合到线性RF功率放大器的电源输出处产生电源电压的并联放大器和开关模式电源转换器。 并联放大器输出与功率放大器电源输出通信。 并联放大器控制开关模式电源转换器的工作，并根据VRAMP信号调节功率放大器电源电压。 并联放大器电路包括开环高频补偿辅助电路，其基于包含在功率电感器的纹波电流中的高频纹波电流的估计来产生高频纹波补偿电流。 高频纹波补偿电流注入到并行放大器电路输出端，以消除功率放大器电源输出端的高频纹波电流。

公开(公告)号：US20110204962A1

公开(公告)日：2011-08-25

申请号：US13013986

申请日：2011-01-26

申请人： Philippe Gorisse ,  Nadim Khlat

发明人： Philippe Gorisse ,  Nadim Khlat

IPC分类号： G05F1/10

CPC分类号： H02M3/07 ,  H02M2003/072

摘要： A charge pump includes an input, an output, and a fixed voltage node; a first capacitor and at least a second capacitor; and a plurality of switches adapted to selectively couple the first capacitor and the at least the second capacitor to the input, the output, and the fixed voltage node. A switch controller is adapted to switch the plurality of switches in response to at least three phase signals to provide fixed gains. A phase generator is adapted to generate the at least three phase signals, wherein at least one of the at least three phase signals has a duty cycle that is different from at least one other of the at least three phase signals. The phase generator is also adapted to adjust the frequency of a clock signal used to generate the at least three phase signals so that a minimum switching frequency is provided.

摘要翻译： 电荷泵包括输入，输出和固定电压节点; 第一电容器和至少第二电容器; 以及多个开关，适于将第一电容器和至少第二电容器选择性地耦合到输入端，输出端和固定电压节点。 开关控制器适于响应于至少三个相位信号切换多个开关以提供固定增益。 相位发生器适于产生至少三个相位信号，其中至少三个相位信号中的至少一个具有不同于至少三个相位信号中的至少另一个的占空比。 相位发生器还适于调整用于产生至少三个相位信号的时钟信号的频率，从而提供最小的开关频率。

公开(公告)号：US08942652B2

公开(公告)日：2015-01-27

申请号：US13602856

申请日：2012-09-04

申请人： Nadim Khlat ,  Michael R. Kay ,  Philippe Gorisse

发明人： Nadim Khlat ,  Michael R. Kay ,  Philippe Gorisse

IPC分类号： H01Q11/12 ,  H04B1/04 ,  H03G1/00 ,  H03F1/02

CPC分类号： H03G1/00 ,  H03F1/0227

摘要： An envelope tracking power supply and transmitter control circuitry are disclosed. The transmitter control circuitry receives a first envelope power supply control signal and a second envelope power supply control signal. The envelope tracking power supply operates in one of a group of operating modes, which includes a first operating mode and a second operating mode. During both the first operating mode and the second operating mode, a first envelope power supply signal is provided to a driver stage based on the first envelope power supply control signal. During the first operating mode, a second envelope power supply signal is provided to a final stage based on the first envelope power supply control signal. However, during the second operating mode, the second envelope power supply signal is provided to the final stage based on the second envelope power supply control signal.

摘要翻译： 公开了一种信封跟踪电源和发射机控制电路。 发射机控制电路接收第一包络电源控制信号和第二包络电源控制信号。 信封跟踪电源以包括第一操作模式和第二操作模式的一组操作模式中的一种操作。 在第一操作模式和第二操作模式期间，基于第一包络电源控制信号将第一包络电源信号提供给驱动器级。 在第一操作模式期间，第二包络电源信号基于第一包络电源控制信号提供到最后级。 然而，在第二操作模式期间，第二包络电源信号基于第二包络电源控制信号提供到最后级。

公开(公告)号：US20110309877A1

公开(公告)日：2011-12-22

申请号：US13116386

申请日：2011-05-26

申请人： Philippe Gorisse

发明人： Philippe Gorisse

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： A high voltage charge-pump having a feedback control loop is disclosed. The high voltage charge-pump includes a plurality of voltage boosting stages, a low voltage input, and at least one clock input. A sensing charge-pump having a voltage detector output has at least one voltage sensing stage that is communicably coupled to at least one of the plurality of voltage boosting stages. A loop filter in the feedback control loop includes a voltage detector input coupled to the voltage detector output, a voltage reference input, and a voltage error output. A voltage controlled oscillator (VCO) with a variable frequency output has a voltage error input coupled to the voltage error output. The feedback control loop also includes at least one driver having a variable frequency input coupled to the variable frequency output and at least one clock output coupled to the at least one clock input.

摘要翻译： 公开了一种具有反馈控制回路的高压电荷泵。 高电压电荷泵包括多个升压级，低电压输入和至少一个时钟输入。 具有电压检测器输出的感测电荷泵具有至少一个电压感测级，其可通信地耦合到多个升压级中的至少一个。 反馈控制回路中的环路滤波器包括耦合到电压检测器输出的电压检测器输入，电压参考输入和电压误差输出。 具有可变频率输出的压控振荡器（VCO）具有耦合到电压误差输出的电压误差输入。 反馈控制回路还包括至少一个驱动器，其具有耦合到可变频率输出的可变频率输入和耦合到至少一个时钟输入的至少一个时钟输出。

公开(公告)号：US08022745B1

公开(公告)日：2011-09-20

申请号：US11856220

申请日：2007-09-17

申请人： David C. Dening ,  Philippe Gorisse

发明人： David C. Dening ,  Philippe Gorisse

IPC分类号： H03K5/08

CPC分类号： H03K17/102

摘要： The present invention is a high voltage semiconductor switch that is formed from a chain of series coupled cascode circuits. In one embodiment, the switch may be a single-throw configuration coupled between an output and a direct current (DC) reference. In an alternate embodiment, the switch may be a double-throw configuration such that the output is switched between either a first DC reference or a second DC reference, such as ground. Each cascode circuit may have clamp circuits to prevent over voltage during switching transitions. The series coupled cascode circuits may be formed using discrete components or on a silicon-on-insulator (SOI) wafer, which may have a Silicon Dioxide insulator layer or a Sapphire insulator layer.

摘要翻译： 本发明是由串联耦合的共源共栅电路链形成的高电压半导体开关。 在一个实施例中，开关可以是耦合在输出和直流（DC）参考之间的单掷配置。 在替代实施例中，开关可以是双掷配置，使得输出在诸如地之间的第一DC参考或第二DC参考之间切换。 每个共源共同电路可以具有钳位电路以在开关转换期间防止过电压。 串联耦合共源共栅电路可以使用分立组件或绝缘体上硅（SOI）晶片形成，其可以具有二氧化硅绝缘体层或蓝宝石绝缘体层。