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    Method, apparatus and system to generate an interrupt by monitoring an external interface
    2.
    发明授权
    Method, apparatus and system to generate an interrupt by monitoring an external interface 有权
    通过监视外部接口产生中断的方法，装置和系统

    公开(公告)号：US07386640B2

    公开(公告)日：2008-06-10

    申请号：US11025381

    申请日：2004-12-28

    Applicant: David C. Lee ,  Steve Kulick ,  Sivakumar Radhakrishnan

    Inventor： David C. Lee ,  Steve Kulick ,  Sivakumar Radhakrishnan

    IPC: G06F3/00

    CPC classification number: G06F13/22 ,  G06F13/24

    Abstract: In some embodiments, a method, apparatus and system to generate an interrupt by monitoring an external interface are presented. In this regard, an interrupt agent is introduced to communicate over a serial interface with an input/output (I/O) extender and to save a relevant status of the I/O extender in a memory. Other embodiments are also disclosed and claimed.

    Abstract translation: 在一些实施例中，呈现通过监视外部接口来产生中断的方法，装置和系统。 在这方面，引入一个中断代理程序通过串行接口与输入/输出（I / O）扩展器进行通信，并将I / O扩展器的相关状态保存在存储器中。 还公开并要求保护其他实施例。

    Dynamic squelch detection power control
    5.
    发明授权
    Dynamic squelch detection power control 失效
    动态静噪检测功率控制

    公开(公告)号：US08352764B2

    公开(公告)日：2013-01-08

    申请号：US12286188

    申请日：2008-09-29

    Applicant: Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

    Inventor： Sin Tan ,  Sivakumar Radhakrishnan ,  Bruce A. Tennant ,  Jasper Balraj ,  Altug Koker

    IPC: G06F1/32 ,  G06F1/26

    CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In one embodiment, the present invention includes power control logic for squelch detection circuitry to enable selective enabling of one or more squelch detection circuits of an interconnect interface in a low power mode. The logic may include a squelch mode control register to select a first mode or a second mode of power control, a second register coupled to the squelch mode control register to receive software settings to indicate which squelch detect circuit(s) to disable in a low power state of the interconnect, and a detector to dynamically detect a logical lane zero of the interconnect in the second mode. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括用于静噪检测电路的功率控制逻辑，以使得能够以低功率模式选择性地启用互连接口的一个或多个静噪检测电路。 逻辑可以包括静噪模式控制寄存器以选择第一模式或第二模式的功率控制;第二寄存器，耦合到静噪模式控制寄存器以接收软件设置，以指示哪个静噪检测电路在低电平中禁用 互连的功率状态，以及用于在第二模式中动态地检测互连的逻辑通道零点的检测器。 描述和要求保护其他实施例。

    STREAM PRIORITY
    7.
    发明申请
    STREAM PRIORITY 有权
    流行优先

    公开(公告)号：US20120042106A1

    公开(公告)日：2012-02-16

    申请号：US13282462

    申请日：2011-10-27

    Applicant: William T. Futral ,  Kenneth C. Creta ,  Sujoy Sen ,  Gregory D. Cummings ,  Sivakumar Radhakrishnan

    Inventor： William T. Futral ,  Kenneth C. Creta ,  Sujoy Sen ,  Gregory D. Cummings ,  Sivakumar Radhakrishnan

    IPC: G06F13/14

    CPC classification number: G06F13/4291

    Abstract: A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

    Abstract translation: 公开了一种用于优先处理事务的系统，方法和装置。 I / O设备可以生成具有流标识符的事务。 事务分类器可以基于事务的流标识符为事务分配优先级。 仲裁者可以基于分配给交易的优先级来选择一个交易进行处理。

    Technique and apparatus for combining partial write transactions
    10.
    发明申请
    Technique and apparatus for combining partial write transactions 审中-公开
    用于组合部分写入事务的技术和装置

    公开(公告)号：US20080235461A1

    公开(公告)日：2008-09-25

    申请号：US11726563

    申请日：2007-03-22

    Applicant: Sin Tan ,  Kai Cheng ,  Rajesh S. Pamujula ,  Sivakumar Radhakrishnan ,  Dhananjay Joshi

    Inventor： Sin Tan ,  Kai Cheng ,  Rajesh S. Pamujula ,  Sivakumar Radhakrishnan ,  Dhananjay Joshi

    IPC: G06F13/28

    CPC classification number: G06F13/1663 ,  G06F13/1668

    Abstract: A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available.

    Abstract translation: 一个桥包括一个建立事务表和写入组合窗口的内存。 每个写入组合窗口与高速缓存行相关联，并被细分为子窗口; 并且每个子窗口与部分高速缓存行相关联。 该桥包括一个控制器，用于确定传入的部分写入事务是否与存储在事务表中的事务冲突。 如果发生冲突，则如果部分写入组合窗口之一可用，则控制器使用写入组合窗口将部分写入事务与另一个部分写入事务组合。 如果没有部分写入组合窗口可用，则控制器向发起部分写入事务的处理器发出重试信号。

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