公开(公告)号：US12272712B2

公开(公告)日：2025-04-08

申请号：US17744664

申请日：2022-05-14

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Chaung-Lin Lai ,  Shu-Ming Chang

IPC: H01L21/48 ,  H01L27/146

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having a chip region and a scribe-line region surrounding the chip region and forming a dielectric layer on an upper surface of the substrate. A dummy structure is formed in the dielectric layer over the scribe-line region of the substrate and extends along edges of the chip region. The dummy structure includes a first stack of dummy metal layers and a second stack of dummy metal layers arranged concentrically from the inside to the outside. The method also includes performing a sawing process on a portion of the dielectric layer that surrounds the dummy structure, so as to form a saw opening through the dielectric layer. At least the first stack of dummy metal layers remains in the dielectric layer after the sawing process is performed.

公开(公告)号：US12237354B2

公开(公告)日：2025-02-25

申请号：US17683917

申请日：2022-03-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Shu-Ming Chang ,  Chaung-Lin Lai

IPC: H01L27/146

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

公开(公告)号：US20250056911A1

公开(公告)日：2025-02-13

申请号：US18751148

申请日：2024-06-21

Applicant: Xintec Inc.

Inventor： Wei-Luen SUEN ,  Chien Wei CHANG ,  Zi-Yu LIAO ,  Jiun-Yen LAI ,  Tsang Yu LIU

IPC: H01L27/146 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: A chip package includes a semiconductor substrate, a light-transmissive plate, a bonding layer, and a light-shielding layer. The bonding layer is located between the semiconductor substrate and the light-transmissive plate. The semiconductor substrate, the bonding layer, and the light-transmissive plate jointly define a sidewall including a first region and a second region. The first region extends from the semiconductor substrate to the light-transmissive plate, and is recessed relative to the second region. The light-shielding layer covers the sidewall and includes an extending portion, a wide portion, and a narrow portion. The extending portion is located on a surface of the semiconductor substrate facing away from the bonding layer. The wide portion is located on the first region of the sidewall. The narrow portion is located on the second region of the sidewall.

公开(公告)号：US11942563B1

公开(公告)日：2024-03-26

申请号：US18327875

申请日：2023-06-01

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC: H01L31/0352 ,  H01L31/02

CPC classification number: H01L31/03529 ,  H01L31/02005

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

公开(公告)号：US11873212B2

公开(公告)日：2024-01-16

申请号：US17184443

申请日：2021-02-24

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Jiun-Yen Lai ,  Hsing-Lung Shen ,  Tsang-Yu Liu

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81B7/0067 ,  B81C1/00317 ,  B81B2203/0353 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0194

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US20230280231A1

公开(公告)日：2023-09-07

申请号：US18175416

申请日：2023-02-27

Applicant: XINTEC INC.

Inventor： Jui Yi KUO ,  Chung Yu LI ,  Yi Fan HU

IPC: G01M3/04

CPC classification number: G01M3/04

Abstract: A leakage detecting assembly includes a sheet leakage detecting module, a signal output unit, and a monitoring control system. The sheet leakage detecting module covers a wielding area or a connection area of a pipeline, and surrounds the pipeline. The sheet leakage detecting module is in direct contact with an outer surface of the pipeline. The signal output unit is electrically connected to the sheet leakage detecting module. The monitoring control system is electrically connected to the signal output unit.

公开(公告)号：US11476293B2

公开(公告)日：2022-10-18

申请号：US16950810

申请日：2020-11-17

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Po-Han Lee

IPC: H01L27/146 ,  H01L23/00

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

公开(公告)号：US11450697B2

公开(公告)日：2022-09-20

申请号：US16581594

申请日：2019-09-24

Applicant: XINTEC INC.

Inventor： Kuei-Wei Chen ,  Chia-Ming Cheng ,  Chia-Sheng Lin

IPC: H01L27/146

Abstract: A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

公开(公告)号：US20220216131A1

公开(公告)日：2022-07-07

申请号：US17560196

申请日：2021-12-22

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Wei-Ming CHIEN

IPC: H01L23/48 ,  H01L29/20 ,  H01L23/498

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.

公开(公告)号：US20210343591A1

公开(公告)日：2021-11-04

申请号：US17373773

申请日：2021-07-13

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/02

Abstract: A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.