公开(公告)号：US20220216131A1

公开(公告)日：2022-07-07

申请号：US17560196

申请日：2021-12-22

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Wei-Ming CHIEN

IPC: H01L23/48 ,  H01L29/20 ,  H01L23/498

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface and a second surface opposite thereto. A gallium nitride (GaN)-based device layer is formed on the first surface of the semiconductor substrate and has source, drain, and gate contact regions. First, second, and third through-substrate vias (TSVs) pass through the semiconductor substrate and are respectively electrically connected to the source, drain, and gate contact regions. An insulating liner layer is formed on the second surface of the semiconductor substrate and extends into the semiconductor substrate to separate the second and third TSVs from the semiconductor substrate. A semiconductor package assembly including the semiconductor device structure is also provided.

公开(公告)号：US20160043123A1

公开(公告)日：2016-02-11

申请号：US14819138

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.

Abstract translation: 半导体结构包括芯片，透光板，间隔物和遮光层。 芯片具有图像传感器，与第一表面相对的第一表面和第二表面。 图像传感器位于第一个表面。 透光板设置在第一表面上并覆盖图像传感器。 间隔物在透光板和第一表面之间，并且围绕图像传感器。 遮光层位于间隔件和图像传感器之间的第一表面上。

公开(公告)号：US20210159350A1

公开(公告)日：2021-05-27

申请号：US17075544

申请日：2020-10-20

Applicant: XINTEC INC.

Inventor： Po-Han LEE ,  Chia-Ming CHENG ,  Wei-Ming CHIEN

IPC: H01L31/0352 ,  H01L31/0216 ,  H01L31/02 ,  H01L31/18

Abstract: A chip package includes a chip and a conductive structure. A first surface of the chip has a photodiode. A second surface of the chip facing away from the first surface has a recess aligned with the photodiode. The conductive structure is located on the first surface of the chip.

公开(公告)号：US20150123231A1

公开(公告)日：2015-05-07

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US20230361144A1

公开(公告)日：2023-11-09

申请号：US18304325

申请日：2023-04-20

Applicant: Xintec Inc.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang Yu LIU ,  Joey LAI

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14623

Abstract: A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.

公开(公告)号：US20170179330A1

公开(公告)日：2017-06-22

申请号：US15451202

申请日：2017-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen SUEN ,  Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L31/18 ,  H01L31/0203 ,  H01L31/0236 ,  H01L31/02

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US20170098678A1

公开(公告)日：2017-04-06

申请号：US15280959

申请日：2016-09-29

Applicant: XINTEC INC.

Inventor： Chaung-Lin LAI ,  Wei-Ming CHIEN

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14685 ,  H01L27/14687 ,  H01L2224/11

Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, wherein the first top surface has a first insulating layer formed thereon, and the sensing chip comprises a sensing device adjacent to the first top surface and a plurality of conductive pads formed within the first insulating and adjacent to the sensing device, and a wiring layer formed on the first bottom surface to respectively connect to each of the conductive pads; and a dam formed on the first insulating layer adjacent to the sensing device.

公开(公告)号：US20240304582A1

公开(公告)日：2024-09-12

申请号：US18431627

申请日：2024-02-02

Applicant: Xintec Inc.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang-Yu LIU

IPC: H01L23/00 ,  H01L23/498 ,  H05K1/18

CPC classification number: H01L24/16 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H05K1/181 ,  H01L2224/11424 ,  H01L2224/11464 ,  H01L2224/13155 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/16225 ,  H01L2924/1431

Abstract: A circuit substrate in a chip package is provided. The circuit substrate includes first and second insulating layers covering opposite first and second surfaces of the semiconductor substrate, respectively. The circuit substrate also includes first and second pads disposed in the first and second insulating layers, respectively, and laterally separated from an opening that extends from the first surface to the second surface of the semiconductor substrate. The circuit substrate further includes first and second under bump metallization (UBM) layers disposed on the first and second pads, respectively. The first UBM layer has a surface protruding above the first insulating layer, and the second UBM layer extends from the second pad onto the second insulating layer, and is partially recessed into the second insulating layer to form a concave surface.

公开(公告)号：US20160218140A1

公开(公告)日：2016-07-28

申请号：US15086809

申请日：2016-03-31

Applicant: XINTEC INC.

Inventor： Wei-Ming CHIEN ,  Chia-Sheng LIN ,  Tsang-Yu LIU ,  Yen-Shih HO

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L21/76898 ,  H01L27/14601 ,  H01L27/14636 ,  H01L33/62

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned photoresist layer is formed on a wafer of the wafer structure. The wafer is etched, such that channels are formed in the wafer, and a protection layer of the wafer structure is exposed through the channels. The protection layer is etched, such that openings aligned with the channels are formed in the protection layer. Landing pads in the protection layer are respectively exposed through the openings and the channels, and the caliber of each of the openings is gradually increased toward the corresponding channel. Side surfaces of the wafer surrounding the channels are etched, such that the channels are expanded to respectively form hollow regions. The caliber of the hollow region is gradually decreased toward the opening, and the caliber of the opening is smaller than that of the hollow region.

Abstract translation: 半导体结构的制造方法包括以下步骤。 在晶片结构的晶片上形成图案化的光致抗蚀剂层。 蚀刻晶片，使得沟槽形成在晶片中，晶片结构的保护层通过沟道露出。 蚀刻保护层，使得在保护层中形成与沟道对准的开口。 保护层中的着陆垫分别通过开口和通道暴露，并且每个开口的口径朝着相应的通道逐渐增加。 蚀刻围绕通道的晶片的侧表面，使得通道膨胀以分别形成中空区域。 中空区域的口径朝向开口逐渐减小，并且开口的口径小于中空区域的口径。

公开(公告)号：US20160181212A1

公开(公告)日：2016-06-23

申请号：US14958672

申请日：2015-12-03

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Po-Han LEE ,  Wei-Ming CHIEN

IPC: H01L23/00 ,  H01L21/78

CPC classification number: H01L24/02 ,  B81C3/00 ,  H01L23/3114 ,  H01L23/315 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02351 ,  H01L2224/02371 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/29011 ,  H01L2224/29082 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/12041 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2924/01028 ,  H01L2924/0105 ,  H01L2924/0781 ,  H01L2924/0549 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0544 ,  H01L2924/0542 ,  H01L2924/0103 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/014 ,  H01L2224/0231 ,  H01L2224/11 ,  H01L2224/83 ,  H01L2224/81

Abstract: A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. A dielectric layer is disposed on the first surface of the substrate and includes a conducting pad structure. A first opening penetrates the substrate and exposes a surface of the conducting pad structure. A second opening is communication with the first opening and penetrates the conducting pad structure. A redistribution layer is conformally disposed on a sidewall of the first opening and the surface of the conducting pad structure and is filled into the second opening. A method for forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有第一表面和与其相对的第二表面的基板。 电介质层设置在衬底的第一表面上并且包括导电焊盘结构。 第一开口穿透衬底并暴露导电垫结构的表面。 第二开口与第一开口连通并穿透导电垫结构。 再分配层保形地设置在第一开口的侧壁和导电垫结构的表面上，并被填充到第二开口中。 还提供了一种用于形成芯片封装的方法。