公开(公告)号：US09972584B2

公开(公告)日：2018-05-15

申请号：US15140199

申请日：2016-04-27

申请人： XINTEC INC.

发明人： Hsing-Lung Shen ,  Jiun-Yen Lai ,  Yu-Ting Huang

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L21/768 ,  H01L23/31 ,  H01L31/0203 ,  H01L21/78 ,  H01L31/0216 ,  H01L33/62 ,  H01L23/48 ,  H01L21/56

CPC分类号： H01L23/564 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/32 ,  H01L22/34 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/481 ,  H01L31/0203 ,  H01L31/02164 ,  H01L33/62 ,  H01L2224/11

摘要： A chip package includes a chip, a dam layer, a carrier substrate and a light shielding passivation layer. The chip has a first surface and a second surface opposite to the first surface, and a side surface is disposed between the first surface and the second surface. The dam layer is disposed on the first surface, and the carrier substrate is disposed on the dam layer. The light shielding passivation layer is disposed under the second surface and extended into the carrier substrate to cover the side surface of the chip.

公开(公告)号：US11309271B2

公开(公告)日：2022-04-19

申请号：US16941486

申请日：2020-07-28

申请人： XINTEC INC.

发明人： Jiun-Yen Lai ,  Chia-Hsiang Chen

IPC分类号： H01L23/00 ,  H01L23/48

摘要： A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

公开(公告)号：US11873212B2

公开(公告)日：2024-01-16

申请号：US17184443

申请日：2021-02-24

申请人： XINTEC INC.

发明人： Wei-Luen Suen ,  Jiun-Yen Lai ,  Hsing-Lung Shen ,  Tsang-Yu Liu

IPC分类号： B81C1/00 ,  B81B7/00

CPC分类号： B81B7/0067 ,  B81C1/00317 ,  B81B2203/0353 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0194

摘要： A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US09761555B2

公开(公告)日：2017-09-12

申请号：US14604525

申请日：2015-01-23

申请人： XINTEC INC.

发明人： Jiun-Yen Lai ,  Yu-Wen Hu ,  Bai-Yao Lou ,  Chia-Sheng Lin ,  Yen-Shih Ho ,  Hsin Kuan

IPC分类号： H01L31/00 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L24/81 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03902 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014

摘要： A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.

公开(公告)号：US11935859B2

公开(公告)日：2024-03-19

申请号：US17588185

申请日：2022-01-28

申请人： XINTEC INC.

发明人： Jiun-Yen Lai ,  Chia-Hsiang Chen

IPC分类号： H01L23/00 ,  H01L23/48

CPC分类号： H01L24/29 ,  H01L23/481 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L2224/29026

摘要： A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

公开(公告)号：US11695199B2

公开(公告)日：2023-07-04

申请号：US17407068

申请日：2021-08-19

申请人： XINTEC INC.

发明人： Jiun-Yen Lai ,  Ming-Chung Chung ,  Wei-Luen Suen

IPC分类号： H01Q1/38 ,  H01Q1/52 ,  H01Q23/00 ,  H01Q1/24

CPC分类号： H01Q1/38 ,  H01Q1/526 ,  H01Q1/243 ,  H01Q23/00

摘要： An antenna device includes a first substrate, a second substrate, an antenna layer, and a redistribution layer. The first substrate has a first surface, a second surface opposite to the first surface, and an inclined sidewall adjoining the first and second surfaces. The second substrate is below the first substrate. The first surface of the first substrate faces toward the second substrate. The antenna layer is located on the first surface of the first substrate. The redistribution layer extends from the second surface of the first substrate to the second substrate along the inclined sidewall of the first substrate, and the redistribution layer has a first section in contact with an end of the antenna layer.

公开(公告)号：US11387201B2

公开(公告)日：2022-07-12

申请号：US17023199

申请日：2020-09-16

申请人： XINTEC INC.

发明人： Po-Han Lee ,  Chia-Ming Cheng ,  Jiun-Yen Lai ,  Ming-Chung Chung ,  Wei-Luen Suen

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/3213

摘要： A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

公开(公告)号：US11137559B2

公开(公告)日：2021-10-05

申请号：US16851099

申请日：2020-04-17

申请人： XINTEC INC.

发明人： Jiun-Yen Lai ,  Yu-Ting Huang ,  Hsing-Lung Shen ,  Tsang-Yu Liu ,  Hui-Hsien Wu

IPC分类号： G02B6/42

摘要： An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

公开(公告)号：US11107759B2

公开(公告)日：2021-08-31

申请号：US17037151

申请日：2020-09-29

申请人： XINTEC INC.

发明人： Wei-Luen Suen ,  Jiun-Yen Lai ,  Hsing-Lung Shen ,  Tsang-Yu Liu

IPC分类号： H01L23/498 ,  H01L21/48

摘要： A chip package includes a lower substrate, a first silicon nitride substrate, a bonding layer, an upper substrate, a first functional layer, a transparent conductive layer, an isolation layer, and a first conductive pad. The supporting layer is located between the lower substrate and the first silicon nitride substrate, and is made of a material including Benzocyclobutene (BCB). The upper substrate is located on the first silicon nitride substrate. The first functional layer is located between the upper substrate and the first silicon nitride substrate. The transparent conductive layer is located on the upper substrate. The isolation layer covers the upper substrate and the transparent conductive layer. The first conductive pad is located in the isolation layer and in electrical contact with the transparent conductive layer.