公开(公告)号：US07945706B2

公开(公告)日：2011-05-17

申请号：US12128634

申请日：2008-05-29

Applicant: An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

Inventor： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

IPC: G06F3/00 ,  G06F13/00

CPC classification number: H04N5/4401 ,  H04N5/46 ,  H04N5/765 ,  H04N21/42615 ,  H04N21/4305 ,  H04N21/436 ,  H04N21/4363

Abstract: The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.

Abstract translation: 本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。 信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。 输入接口包括一组共享输入端子，一组第一分离输入端子，用于接收与该组共享输入端子对应的第一传输规格的输入信号，以及一组用于接收输入信号的第二单独输入端子 对应于具有该组共享输入端的第二传输规范。 接口电路包括耦合到用于提供控制信号的输入接口的控制电路，以及耦合到输入接口和控制电路的处理模块，用于根据控制信号处理输入信号以产生输出信号。

公开(公告)号：US20100238159A1

公开(公告)日：2010-09-23

申请号：US12726931

申请日：2010-03-18

Applicant: Wen-Hsia KUNG ,  Tzuo-Bo LIN ,  Chia-Lung HUNG ,  Yu-Pin CHOU

Inventor： Wen-Hsia KUNG ,  Tzuo-Bo LIN ,  Chia-Lung HUNG ,  Yu-Pin CHOU

IPC: G06F3/038 ,  H03K3/00

CPC classification number: H03K5/151 ,  H03K19/0008

Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.

Abstract translation: 差分信号发生装置包括控制电路和接收单端信号的差分信号驱动器。 当源信号符合第一预定义状态时，控制电路接收源信号并产生对应于第一模式的控制信号，并且当源信号符合第二预定义状态时，控制电路对应于第二模式。 源信号的变化与单端信号的信号内容有关。 差分信号驱动器耦合到控制单元以从其接收控制信号。 当控制信号对应于第一模式时，差分信号驱动器根据单端信号输出差分信号。 当控制信号对应于第二模式时，差分信号驱动器输出非差分信号输出。

公开(公告)号：US20100188574A1

公开(公告)日：2010-07-29

申请号：US12692389

申请日：2010-01-22

Applicant: Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

Inventor： Chia-Lung HUNG ,  Tzuo-Bo Lin ,  Hsien-Chun Chang ,  Yu-Pin Chou

IPC: H04N9/64 ,  H04N5/04

CPC classification number: H04N7/0105 ,  H04N7/0132

Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.

Abstract translation: 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

公开(公告)号：US07679454B2

公开(公告)日：2010-03-16

申请号：US11874209

申请日：2007-10-18

Applicant: Chi-Kung Kuan ,  Yu-Pin Chou ,  Yi-Teng Chen

Inventor： Chi-Kung Kuan ,  Yu-Pin Chou ,  Yi-Teng Chen

IPC: H03L7/00

CPC classification number: H03L7/087 ,  H03L7/081 ,  H03L7/1976 ,  H03L7/23

Abstract: A phase-locked loop (PLL) including a digital PFD, a digital loop filter, a decision circuit, a fractional-N PLL, and a frequency divider is provided. The digital PFD generates a first detection signal according to the phase error or frequency difference between an input signal and a feedback signal. The digital loop filter generates a first control signal according to the first detection signal. The decision circuit generates a divisor value according to the first control signal. The fractional-N PLL generates an oscillation signal according to the divisor value and a reference signal. The frequency divider divides the oscillation signal to produce the feedback signal. The fractional-N PLL includes a fractional-N frequency divider for generating a frequency-divided signal for use in tracking the reference signal according to the divisor value by employing phase swallow means.

Abstract translation: 提供了包括数字PFD，数字环路滤波器，判决电路，分数N PLL和分频器的锁相环（PLL）。 数字PFD根据输入信号和反馈信号之间的相位误差或频率差产生第一检测信号。 数字环路滤波器根据第一检测信号产生第一控制信号。 决定电路根据第一控制信号产生除数值。 分数N PLL根据除数值和参考信号产生振荡信号。 分频器分频振荡信号产生反馈信号。 分数N PLL包括分数N分频器，用于通过采用相位吞吐装置，根据除数值产生用于跟踪参考信号的分频信号。

公开(公告)号：US07663416B2

公开(公告)日：2010-02-16

申请号：US11847343

申请日：2007-08-30

Applicant: Hsu-Jung Tung ,  Chi-Kung Kuan ,  Yu-Pin Chou

Inventor： Hsu-Jung Tung ,  Chi-Kung Kuan ,  Yu-Pin Chou

IPC: H03L7/06

CPC classification number: H04N7/56 ,  H04N5/04 ,  H04N5/126 ,  H04N5/602 ,  H04N21/2368 ,  H04N21/4305 ,  H04N21/4341 ,  H04N21/439

Abstract: An apparatus for generating an audio output clock is disclosed. The apparatus at least includes a plurality of dividers and a frequency synthesizer. The apparatus utilizes the dividers to achieve dispersive frequency-division operations such that the anti-noise ability of the apparatus can be improved. In addition, the apparatus also utilizes dynamic phase adjustment to increase accuracy of the frequency of the audio output clock.

Abstract translation: 公开了一种用于产生音频输出时钟的装置。 该装置至少包括多个分频器和频率合成器。 该装置利用分频器实现色散分频操作，从而可以提高装置的抗噪声能力。 此外，该装置还利用动态相位调整来提高音频输出时钟频率的精度。

公开(公告)号：US07580044B2

公开(公告)日：2009-08-25

申请号：US11163887

申请日：2005-11-02

Applicant: Hsu-Jung Tung ,  Chun-Hsing Hsieh ,  Yu-Pin Chou ,  Hsien-Chun Chang

Inventor： Hsu-Jung Tung ,  Chun-Hsing Hsieh ,  Yu-Pin Chou ,  Hsien-Chun Chang

IPC: G09G5/02

CPC classification number: G09G3/2055

Abstract: A method for dithering an image is disclosed, which includes: storing a plurality of dithering parameters corresponding to a predetermined function for a predetermined input intensity range; and dithering pixels of the predetermined input intensity range according to the plurality of dithering parameters.

Abstract translation: 公开了一种用于抖动图像的方法，其包括：在预定的输入强度范围内存储对应于预定功能的多个抖动参数; 以及根据多个抖动参数的预定输入强度范围的抖动像素。

公开(公告)号：US20080297511A1

公开(公告)日：2008-12-04

申请号：US12128372

申请日：2008-05-28

Applicant: Yu-Pin CHOU ,  Szu-Ping CHEN ,  Yu Jen LIN

Inventor： Yu-Pin CHOU ,  Szu-Ping CHEN ,  Yu Jen LIN

IPC: G06T17/00 ,  G09G5/02

CPC classification number: G06T1/60 ,  G09G3/28 ,  G09G3/36 ,  G09G5/005 ,  G09G2310/08 ,  G09G2340/0414 ,  G09G2340/0421

Abstract: The invention discloses a mode detection circuit and a method thereof, for detecting an image signal, the image signal includes a horizontal resolution and the vertical resolution. The mode detection circuit includes a measuring unit, a calculation unit, and a decision unit. The measuring unit receives a clock signal and is used to count the clock signal to output a first counting value and the second counting value. The calculation unit is used to perform the calculation with the first counting value and the second counting value and thereby outputting a calculating value, wherein the calculating value outputted by the calculation unit is corresponding to the ratio of the first counting value to the second counting value. The decision unit is used to determine the horizontal resolution or the vertical resolution according to the calculating value.

Abstract translation: 本发明公开了一种模式检测电路及其方法，用于检测图像信号，图像信号包括水平分辨率和垂直分辨率。 模式检测电路包括测量单元，计算单元和判定单元。 测量单元接收时钟信号，并用于对时钟信号进行计数以输出第一计数值和第二计数值。 计算单元用于执行具有第一计数值和第二计数值的计算，从而输出计算值，其中由计算单元输出的计算值对应于第一计数值与第二计数值的比率 。 决策单元用于根据计算值确定水平分辨率或垂直分辨率。

公开(公告)号：US07382163B2

公开(公告)日：2008-06-03

申请号：US10820473

申请日：2004-04-07

Applicant: Yu-Pin Kuo ,  Yu-Pin Chou ,  Shu-Rong Tong

Inventor： Yu-Pin Kuo ,  Yu-Pin Chou ,  Shu-Rong Tong

IPC: G01R25/00

CPC classification number: H03D13/004

Abstract: A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a phase error judgment signal according to the first input signal and the second input signal; and a reset unit outputting a first reset signal to reset the phase error detector, and outputting a second reset signal to reset the phase error judgment unit, according to the phase error judgment signal.

Abstract translation: 相位频率检测器包括：相位误差检测器，输出根据第一输入信号和第二输入信号的相位误差信号; 相位误差判断单元，根据第一输入信号和第二输入信号输出相位误差判定信号; 以及复位单元，输出第一复位信号以复位相位误差检测器，并且根据相位误差判断信号输出第二复位信号以复位相位误差判断单元。

公开(公告)号：US07372298B2

公开(公告)日：2008-05-13

申请号：US11277361

申请日：2006-03-24

Applicant: Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

Inventor： Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

IPC: H03K19/173 ,  H03K19/00

CPC classification number: G06F1/22 ,  H03K19/1732

Abstract: A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

Abstract translation: 公开了一种具有可调节引脚排列功能的芯片。 芯片包括第一引脚，第二引脚，逻辑电路和选择电路。 逻辑电路包括第一端口和第二端口。 耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或 第二个港口。

公开(公告)号：US20080106641A1

公开(公告)日：2008-05-08

申请号：US11936058

申请日：2007-11-06

Applicant: Yu-Pin Chou

Inventor： Yu-Pin Chou

IPC: H04N7/01

CPC classification number: H04N7/0122 ,  G09G3/20 ,  G09G2310/0232 ,  G09G2340/0407 ,  G09G2340/0442 ,  G09G2340/0464

Abstract: A method for controlling a display device is disclosed. The method includes receiving an input video image having a plurality of active scan lines, controlling the display device to display a plurality of background scan lines on a first display area with a first scan line frequency, and controlling the display device to display an output image on a second display area with a second scan line frequency. A second aspect ratio of the output image is substantially equal to a first aspect ratio of the input video image. The second scan line frequency is substantially lower than the first scan line frequency.

Abstract translation: 公开了一种用于控制显示装置的方法。 该方法包括：接收具有多条主动扫描线的输入视频图像，控制显示装置在具有第一扫描线频率的第一显示区域上显示多条背景扫描线，并且控制显示装置显示输出图像 在具有第二扫描线频率的第二显示区域上。 输出图像的第二宽高比基本上等于输入视频图像的第一宽高比。 第二扫描线频率基本上低于第一扫描线频率。