公开(公告)号：US6043148A

公开(公告)日：2000-03-28

申请号：US61613

申请日：1998-04-16

Applicant: Yuan-Ching Peng ,  Lih-Juann Chen ,  Yu-Ru Yang ,  Win-Yi Hsieh ,  Yong-Fen Hsieh

Inventor： Yuan-Ching Peng ,  Lih-Juann Chen ,  Yu-Ru Yang ,  Win-Yi Hsieh ,  Yong-Fen Hsieh

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76856 ,  H01L21/76843

Abstract: A method of fabricating a metal plug. On a semiconductor substrate comprising a MOS device, a dielectric layer, and a via hole penetrating though the dielectric layer, a conformal titanium layer is formed on the dielectric layer and the via hole. A low temperature annealing is formed in a nitrogen environment, so that a surface of the titanium layer is transformed into a first thin titanium nitride layer. A conformal second titanium nitride layer is formed on the first thin titanium nitride layer by using collimator sputtering. A metal layer is formed and etched back on the second titanium nitride layer to form a metal plug.

Abstract translation: 一种制造金属插头的方法。 在包括MOS器件，电介质层和穿过电介质层的通孔的半导体衬底上，在电介质层和通孔上形成共形钛层。 在氮气环境中形成低温退火，使得钛层的表面转变为第一薄氮化钛层。 通过使用准直器溅射在第一薄氮化钛层上形成保形第二氮化钛层。 在第二氮化钛层上形成金属层并回蚀​​刻以形成金属塞。

公开(公告)号：US08937353B2

公开(公告)日：2015-01-20

申请号：US12714796

申请日：2010-03-01

Applicant: Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

Inventor： Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。

公开(公告)号：US20120322246A1

公开(公告)日：2012-12-20

申请号：US13162813

申请日：2011-06-17

Applicant: Sheng-Hsiung WANG ,  Hsien-Chin LIN ,  Yuan-Ching PENG ,  Chia-Pin LIN ,  Fan-Yi HSU ,  Ya-Jou HSIEH

Inventor： Sheng-Hsiung WANG ,  Hsien-Chin LIN ,  Yuan-Ching PENG ,  Chia-Pin LIN ,  Fan-Yi HSU ,  Ya-Jou HSIEH

IPC: H01L21/20 ,  H01L21/311 ,  H01L21/3205

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L29/66545

Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

Abstract translation: 一种用于制造集成电路器件的方法，包括提供具有第一区域和第二区域的衬底。 在第一区域和第二区域中的衬底上形成介电层。 在电介质层上形成牺牲栅极层。 对牺牲栅极层和电介质层进行图案化以在第一和第二区域中形成栅极叠层。 在第一和第二区域内的栅堆叠内形成ILD层。 去除第一和第二区域中的牺牲栅极层。 在第一区域中的介电层上形成保护膜; 然后除去第二区域中的电介质层。

公开(公告)号：US20110210393A1

公开(公告)日：2011-09-01

申请号：US12714796

申请日：2010-03-01

Applicant: Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

Inventor： Hung-Kai Chen ,  Hsien-Hsin Lin ,  Chia-Pin Lin ,  Chien-Tai Chan ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。

公开(公告)号：US20110079820A1

公开(公告)日：2011-04-07

申请号：US12572743

申请日：2009-10-02

Applicant: Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

Inventor： Kao-Ting Lai ,  Da-Wen Lin ,  Hsien-Hsin Lin ,  Yuan-Ching Peng ,  Chi-Hsi Wu

IPC: H01L29/165 ,  H01L21/30 ,  H01L29/78

CPC classification number: H01L21/3247 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract translation: 一种方法包括提供包括衬底材料的衬底，在衬底上方的栅极电介质膜和与栅极电介质膜相邻的第一间隔物。 间隔物具有与基底的表面接触的第一部分和与栅极电介质膜的一侧接触的第二部分。 在与衬垫相邻的衬底的区域中形成凹部。 凹部由基底材料的第一侧壁限定。 第一侧壁的至少一部分位于间隔件的至少一部分的下面。 衬垫材料位于衬垫的第一部分下面被回流，使得限定凹陷的衬底材料的第一侧壁的顶部基本上与栅极电介质膜和间隔物之间​​的边界对齐。 凹陷部分填充有压力源材料。

公开(公告)号：US20060120149A1

公开(公告)日：2006-06-08

申请号：US11119052

申请日：2005-04-29

Applicant: Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

Inventor： Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

IPC: G11C11/14

CPC classification number: G11C11/15 ,  G11C5/063

Abstract: A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

Abstract translation: 本文公开的磁性随机存取存储器（MRAM）装置包括具有磁阻（MR）堆叠的磁存储器单元阵列。 MRAM阵列还包括耦合到MR堆叠的一系列位线和字线。 阵列布局通过增加沿着公共导体的相邻MR堆叠之间的距离而不增加MRAM阵列的总体布局面积来提供相邻存储器单元之间减少的串扰。 公开了几个实施例，其中相邻MR堆叠被偏移，使得MR堆叠交错。 例如，耦合到公共字线或公共位线的MR堆叠组可以交错。 交错布局提供了对于给定MRAM阵列区域的相邻MR堆叠之间的距离增加，从而导致例如在写入操作期间串扰的减少。

公开(公告)号：US06730937B2

公开(公告)日：2004-05-04

申请号：US09748834

申请日：2000-12-26

Applicant: Yuan-Tung Dai ,  Yuan-Ching Peng ,  Chien-Chih Chen

Inventor： Yuan-Tung Dai ,  Yuan-Ching Peng ,  Chien-Chih Chen

IPC: H01L3300

CPC classification number: H01L27/156 ,  H01L25/0753 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A full-color LED display includes red, green and blue LED elements. A first substrate is used to form red and green LED elements which are then covered by a first passivation layer. A second substrate is bonded to the passviation layer and polished as a thin substrate layer. A blue LED element is fabricated on the thin substrate layer. The three LED elements are then covered by a second passivation layer to construct a full-color LED device. A full-color, high resolution and high brightness LED display is formed by a plurality of full-color LED devices arranged in rows and columns in a matrix form.

Abstract translation: 全彩LED显示屏包括红色，绿色和蓝色LED元件。 第一衬底用于形成红色和绿色LED元件，然后被第一钝化层覆盖。 第二衬底被结合到钝化层并被抛光为薄的衬底层。 在薄的衬底层上制造蓝色LED元件。 然后，三个LED元件被第二钝化层覆盖以构成全色LED装置。 全彩色，高分辨率和高亮度LED显示器由以矩阵形式排列成行和列的多个全色LED装置形成。

公开(公告)号：US09349657B2

公开(公告)日：2016-05-24

申请号：US13162813

申请日：2011-06-17

Applicant: Sheng-Hsiung Wang ,  Hsien-Chin Lin ,  Yuan-Ching Peng ,  Chia-Pin Lin ,  Fan-Yi Hsu ,  Ya-Jou Hsieh

Inventor： Sheng-Hsiung Wang ,  Hsien-Chin Lin ,  Yuan-Ching Peng ,  Chia-Pin Lin ,  Fan-Yi Hsu ,  Ya-Jou Hsieh

IPC: C23C16/24 ,  H01L21/20 ,  H01L21/36 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L29/66545

Abstract: A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

Abstract translation: 一种用于制造集成电路器件的方法，包括提供具有第一区域和第二区域的衬底。 在第一区域和第二区域中的衬底上形成介电层。 在电介质层上形成牺牲栅极层。 对牺牲栅极层和电介质层进行图案化以在第一和第二区域中形成栅极堆叠。 在第一和第二区域内的栅堆叠内形成ILD层。 去除第一和第二区域中的牺牲栅极层。 在第一区域中的介电层上形成保护膜; 然后除去第二区域中的电介质层。

公开(公告)号：US20110223753A1

公开(公告)日：2011-09-15

申请号：US12724157

申请日：2010-03-15

Applicant: Sheng-Hsiung Wang ,  Fu-Kai Yang ,  Yuan-Ching Peng ,  Chi-Cheng Hung

Inventor： Sheng-Hsiung Wang ,  Fu-Kai Yang ,  Yuan-Ching Peng ,  Chi-Cheng Hung

IPC: H01L21/3065 ,  H01L21/28

CPC classification number: H01L21/31144 ,  H01L21/28017 ,  H01L21/31116 ,  H01L29/66795

Abstract: A method of removing a hard mask during fabrication of semiconductor devices is provided. A protective layer, such as a bottom anti-reflective coating (BARC) layer or other dielectric layer, is formed over structures formed on a substrate, wherein spacers are formed alongside the structures. In an embodiment, the structures are gate electrodes having a hard mask formed thereon and the spacers are spacers formed alongside the gate electrodes. A photoresist layer is formed over the protective layer, and the photoresist layer may be patterned to remove a portion of the photoresist layer over portions of the protective layer. Thereafter, an etch-back process is performed, such that the protective layer adjacent to the spacers remains to substantially protect the spacers. The hard mask is then removed while the protective layer protects the spacers.

Abstract translation: 提供了在制造半导体器件期间去除硬掩模的方法。 在衬底上形成的结构上形成诸如底部抗反射涂层（BARC）层或其它电介质层的保护层，其中间隔物沿着结构形成。 在一个实施例中，结构是具有形成在其上的硬掩模的栅电极，并且间隔物是与栅电极一起形成的间隔物。 在保护层上形成光致抗蚀剂层，并且可以对光致抗蚀剂层进行图案化以在保护层的部分上去除光致抗蚀剂层的一部分。 此后，执行回蚀处理，使得与间隔物相邻的保护层保持基本上保护间隔物。 然后去除硬掩模，同时保护层保护间隔物。

公开(公告)号：US07663237B2

公开(公告)日：2010-02-16

申请号：US11320512

申请日：2005-12-27

Applicant: Yuan-Ching Peng ,  Chloe Hsin-yi Chen ,  David Hsu-Wei Lwu ,  Shyue-Shyh Lin ,  Wei-Ming Chen

Inventor： Yuan-Ching Peng ,  Chloe Hsin-yi Chen ,  David Hsu-Wei Lwu ,  Shyue-Shyh Lin ,  Wei-Ming Chen

IPC: H01L23/48

CPC classification number: H01L27/11 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/7833

Abstract: A semiconductor structure and a method of forming the same using replacement gate processes are provided. The semiconductor structure includes a butted contact coupling a source/drain region, or a silicide on the source/drain region, of a first transistor and a gate extension. The semiconductor structure further includes a contact pad over the source/drain region of the first transistor and electrically coupled to the source/drain region. The addition of the contact pad reduces the contact resistance and the possibility that an open circuit is formed between the butted contact and the source/drain region. The contact pad preferably has a top surface substantially leveled with a top surface of the gate extension.

Abstract translation: 提供半导体结构及其使用替代栅极工艺的方法。 半导体结构包括耦合第一晶体管和栅极延伸的源极/漏极区域或源极/漏极区域上的硅化物的对接触点。 半导体结构还包括在第一晶体管的源极/漏极区域上的电连接到源极/漏极区域的接触焊盘。 接触焊盘的添加减小了接触电阻以及在对接触点和源极/漏极区域之间形成开路的可能性。 接触垫优选地具有基本上与门延伸部的顶表面平齐的顶表面。