Extending measured boot for secure link establishment

    公开(公告)号:US12235967B1

    公开(公告)日:2025-02-25

    申请号:US18323868

    申请日:2023-05-25

    Abstract: A modified measured boot approach is utilized for establishing a secure communication link between two devices. Each device may execute a respective boot process until the device reaches the stage responsible for establishing the communication link with the other device. Each device may exchange its respective self-signed certificate and extend its certificate chain with the self-signed certificate received from the other device. A secure link can be established using the public key of the other device as a based key for a key exchange protocol.

    SECURE BOOTING OF VIRTUALIZATION MANAGERS
    3.
    发明申请

    公开(公告)号:US20190311128A1

    公开(公告)日:2019-10-10

    申请号:US16435391

    申请日:2019-06-07

    Abstract: A multi-phase boot operation of a virtualization manager at a virtualization host is initiated at an offload card. In a first phase of the boot, a security key stored in a tamper-resistant location of the offload card is used. In a second phase, firmware programs are measured using a security module, and a first version of a virtualization coordinator is instantiated at the offload card. The first version of the virtualization coordinator obtains a different version of the virtualization coordinator and launches the different version at the offload card. Other components of the virtualization manager (such as various hypervisor components that do not run at the offload card) are launched by the different version of the virtualization controller.

    Non-coherent and coherent connections in a multi-chip system

    公开(公告)号:US11880327B1

    公开(公告)日:2024-01-23

    申请号:US17643132

    申请日:2021-12-07

    CPC classification number: G06F13/4027

    Abstract: A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.

    MULTIPLE PORT EMULATION
    5.
    发明公开

    公开(公告)号:US20230221971A1

    公开(公告)日:2023-07-13

    申请号:US18186748

    申请日:2023-03-20

    CPC classification number: G06F13/4221 G06F13/24 G06F13/105

    Abstract: Multiple independent endpoint devices can be emulated using a single system on chip (SoC) device. Such a SoC can have multiple cores that can emulate ports according to a specified protocol, such as the peripheral component interconnect express (PCIe) protocol useful for data communications. An emulation agent can manage various aspects of these emulated endpoint devices in software, including serving interrupts for relevant emulated devices according to a determined priority scheme. Interrupts can be registered for each device, and data structures allocated dynamically for a determined number and type(s) of PCIe endpoint devices to be emulated. Each PCIe core on the SoC can function as a separate PCIe endpoint device endpoint for communicating with one or more hosts or other such devices.

    Combination boot for an integrated circuit

    公开(公告)号:US12223052B1

    公开(公告)日:2025-02-11

    申请号:US17695630

    申请日:2022-03-15

    Abstract: A boot process for a computing device, such as integrated circuit, includes security features that are inaccessible during certain operation modes. An image including permission to access those security features is received during the boot process and may be verified using one or more keys. In operation, access to the security features is permitted during the operation modes after the image is verified. Such an approach enables a boot process to permit access to certain features after receipt and verification of different images.

    Secure monitors for memory page protection

    公开(公告)号:US12216921B1

    公开(公告)日:2025-02-04

    申请号:US17710489

    申请日:2022-03-31

    Abstract: Technologies are disclosed for using hardware-embedded monitors to monitor pages of local memory and detect attribute violations or other unauthorized operations relating to the memory. The attribute violations may include mismatches of attributes (e.g., designating a page as writeable versus executable or vice versa) in entries in a translation buffer that point to a same physical address or other mismatches between designations of attributes for a page in physical and virtual space. Responsive to detecting a violation, an alert or other mitigation protocol, which may include an audit of activities surrounding the violation, may be performed.

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