-
公开(公告)号：US11444746B1
公开(公告)日：2022-09-13
申请号：US17303757
申请日：2021-06-07
Applicant: Analog Devices, Inc.
Inventor： John Kenney , Robert Schell
Abstract: Apparatus and methods for phasing detection of asynchronous dividers are provided herein. In certain embodiments, a clock and data recovery system includes a first divider that outputs a first divided clock signal, a second divider that outputs a second divided clock signal, and an asynchronous clock phasing detection circuit that generates a detection signal indicating a relative phase difference between the first divided clock signal and the second divided clock signal. The asynchronous clock phasing detection circuit includes a quantization and logic circuit that generates an output signal indicating when the first divided clock signal and the second divided clock signal are in different states, an oscillator that outputs a control clock signal, a first counter controlled by the control clock signal and configured to count the output signal, and a control circuit that processes a first count signal from the first counter to generate the detection signal.
-
公开(公告)号：US20140086364A1
公开(公告)日：2014-03-27
申请号：US13629170
申请日：2012-09-27
Applicant: ANALOG DEVICES, INC.
Inventor： Robert Schell , John Kenney , Wei-Hung Chen
CPC classification number: H03H7/06 , H03B27/00 , H03H7/20 , H03H7/21 , H03H11/22 , H03H2007/0192 , H04L7/0025 , H04L7/033
Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.
Abstract translation: 提供了正交时钟信号生成的装置和方法。 在某些实现中，正交时钟信号发生器包括正弦整形滤波器和多相滤波器。 正弦整形滤波器可以接收诸如正方形或矩形波的输入时钟信号，并且可以对输入时钟信号进行滤波以产生正弦时钟信号。 此外，多相滤波器可以使用正弦时钟信号来产生可以具有大约九十度的相位差的同相（I）和正交相（Q）时钟信号。 在某些配置中，由多相滤波器产生的同相和正交相位时钟信号可由缓冲电路缓冲，以产生适合在时钟和数据恢复中使用的同相和正交相位正弦参考时钟信号（CDR ）系统。
-
公开(公告)号：US10033555B2
公开(公告)日：2018-07-24
申请号：US15265275
申请日：2016-09-14
Applicant: Analog Devices, Inc.
Inventor： Robert Schell
Abstract: A system can be configured to control an equalizer circuit to equalize a data signal without requiring prior knowledge of the data signal's data rate. In an example, the system includes an equalizer circuit configured to equalize a data signal based on an equalizer control signal to produce an equalized signal, and a pattern detector configured to detect a specified data pattern in the equalized signal at each of multiple sampling rates. A control circuit can be configured to generate a preferred equalization control signal based on a sampling rate, selected from the multiple sampling rates, at which the pattern detector detects the specified data pattern in the equalized signal.
-
公开(公告)号：US20180076985A1
公开(公告)日：2018-03-15
申请号：US15265275
申请日：2016-09-14
Applicant: Analog Devices, Inc.
Inventor： Robert Schell
CPC classification number: H04L25/03057 , H04L7/027 , H04L25/0262 , H04L25/03019 , H04L25/0305 , H04L25/03159 , H04L25/03885 , H04L2025/03592 , H04L2025/03764
Abstract: A system can be configured to control an equalizer circuit to equalize a data signal without requiring prior knowledge of the data signal's data rate. In an example, the system includes an equalizer circuit configured to equalize a data signal based on an equalizer control signal to produce an equalized signal, and a pattern detector configured to detect a specified data pattern in the equalized signal at each of multiple sampling rates. A control circuit can be configured to generate a preferred equalization control signal based on a sampling rate, selected from the multiple sampling rates, at which the pattern detector detects the specified data pattern in the equalized signal.
-
Patent Agency Ranking
公开(公告)号：US11509338B2
公开(公告)日：2022-11-22
申请号：US17204618
申请日：2021-03-17
Applicant: Analog Devices, Inc.
Inventor： John Kenney , Robert Schell , Rahul Vemuri
IPC: H04B1/12
Abstract: Systems and methods are provided for optimizing offset compensation in a receiver with multiple offset compensation D/A converters. At each stage where offset cancellation is applied, there is a fan-out of two or more. At the final stage, comparator offset compensation codes are summed and compared against a digital reference. In one version the digital reference is zero. A second implementation has a non-zero digital reference which is the sum of comparator offsets stored from start up. The difference between the sum of offsets and digital reference is applied to a digital accumulator. The most significant bits of the digital accumulator are applied to a digital D/A converter, which cancel analog offsets in an intermediate stage of amplifiers. The summation of offsets feeding into an accumulator is implemented for all preceding stages.
-
公开(公告)号：US10177897B2
公开(公告)日：2019-01-08
申请号：US15287812
申请日：2016-10-07
Applicant: ANALOG DEVICES, INC.
Inventor： Robert Schell , Robert D. Bishop
Abstract: Serial data transfer uses ever increasing transmission rates. The data transfer rate of a clock-and-data recovery (CDR) deserializer can be increased by using multiple independent sampler blocks that process serial input data in parallel. For this purpose, the clock output signals from the various independent blocks are first mutually aligned in proper order using a lower speed clock, and subsequently offset from one another such that sampling instances of the various sampler blocks are interleaved. Digitized data words corresponding to common input data and outputted by the various sampler blocks are compared after alignment of the clock output signals to correct additional timing misalignment between the multiple sampler blocks. The digitized data words need only be aligned once or at most infrequently after the clock output signals are aligned, since the additional timing misalignment is caused mainly path delays that are substantially invariant over time.
-
公开(公告)号：US20150288545A1
公开(公告)日：2015-10-08
申请号：US14552296
申请日：2014-11-24
Applicant: ANALOG DEVICES, INC.
Inventor： Robert Schell , Jesse Bankman
IPC: H04L25/03
CPC classification number: H04L25/03057 , H04L25/03012 , H04L25/03885
Abstract: Apparatus and methods for continuous-time equalization are provided. In one aspect, an apparatus includes an integrator configured to track and process an asynchronous input signal according to actual or approximated frequency-dependent subtraction. The apparatus further includes a comparator or subtractor configured to compare a threshold, output by the integrator, with the asynchronous input signal. In various embodiments, the integrator can include a leaky integrator configured to apply a transform in the form 1/(1+s/γ), wherein s can be adjusted based on the complex angular frequency of the asynchronous input signal. In various embodiments, the integrator can include a programmable network having a resistance R and a capacitance C, and γ can include 1/(RC). In various embodiments, the integrator can include one or more programmable current sources configured to adjust a level of boost in said frequency-dependent subtraction.
Abstract translation: 提供了连续时间均衡的装置和方法。 一方面，一种装置包括积分器，其被配置为根据实际或近似的频率相关减法跟踪和处理异步输入信号。 该装置还包括比较器或减法器，其被配置为将由积分器输出的阈值与异步输入信号进行比较。 在各种实施例中，积分器可以包括被配置为以1 /（1 + s /γ）形式应用变换的泄漏积分器，其中可以基于异步输入信号的复角频率来调整s。 在各种实施例中，积分器可以包括具有电阻R和电容C的可编程网络，并且γ可以包括1 /（RC）。 在各种实施例中，积分器可以包括一个或多个可编程电流源，其配置成在所述频率相关减法中调整升压电平。
-
公开(公告)号：US08760209B2
公开(公告)日：2014-06-24
申请号：US13629170
申请日：2012-09-27
Applicant: Analog Devices, Inc.
Inventor： Robert Schell , John Kenney , Wei-Hung Chen
CPC classification number: H03H7/06 , H03B27/00 , H03H7/20 , H03H7/21 , H03H11/22 , H03H2007/0192 , H04L7/0025 , H04L7/033
Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, a quadrature clock signal generator includes a sine-shaping filter and a polyphase filter. The sine-shaping filter can receive an input clock signal such as a square or rectangular wave and can filter the input clock signal to generate a sinusoidal clock signal. Additionally, the polyphase filter can use the sinusoidal clock signal to generate in-phase (I) and quadrature-phase (Q) clock signals, which can have a phase difference of about ninety degrees. In certain configurations, the in-phase and quadrature-phase clock signals generated by the polyphase filter can be buffered by a buffer circuit to generate in-phase and quadrature-phase sinusoidal reference clock signals suitable for use in a clock and data recover (CDR) system.
Abstract translation: 提供了正交时钟信号生成的装置和方法。 在某些实现中，正交时钟信号发生器包括正弦整形滤波器和多相滤波器。 正弦整形滤波器可以接收诸如正方形或矩形波的输入时钟信号，并且可以对输入时钟信号进行滤波以产生正弦时钟信号。 此外，多相滤波器可以使用正弦时钟信号来产生可以具有大约九十度的相位差的同相（I）和正交相（Q）时钟信号。 在某些配置中，由多相滤波器产生的同相和正交相位时钟信号可由缓冲电路缓冲，以产生适合在时钟和数据恢复中使用的同相和正交相位正弦参考时钟信号（CDR ）系统。
-
9.发明授权公开(公告)号：US08754678B1
公开(公告)日：2014-06-17
申请号：US13835598
申请日：2013-03-15
Applicant: Analog Devices, Inc.
Inventor： Robert Schell
Abstract: Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.
Abstract translation: 提供了正交时钟信号生成的装置和方法。 在某些实现中，一种装置包括被配置为接收同相时钟信号，正交相位时钟信号和反相控制信号的可逆正弦整形滤波器。 可逆正弦整形滤波器还被配置为对同相和正交相位时钟信号进行滤波以产生正弦同相和正交相位时钟信号。 可逆正弦整形滤波器还被配置为基于反相控制信号选择性地反相同相和正交相位时钟信号中的一个或两者。 该装置还包括相位插值器，其被配置为基于选择性反转的正弦同相时钟信号和正交相位正弦时钟信号的加权和产生内插时钟信号。 同相时钟信号和正交相位时钟信号具有正交相位关系。
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.019 seconds)
