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1.发明授权System and method of improving stability of continuous-time delta-sigma modulators 有权提高连续时间Δ-Σ调制器稳定性的系统和方法公开(公告)号：US09148168B2
公开(公告)日：2015-09-29
申请号：US14065732
申请日：2013-10-29
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Zhao Li , David Alldred
CPC classification number: H03M3/368 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/38 , H03M3/424 , H03M3/454
Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.
Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。
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2.发明申请SYSTEM AND METHOD OF IMPROVING STABILITY OF CONTINUOUS-TIME DELTA-SIGMA MODULATORS 有权连续时间三角形调制器稳定性的系统和方法公开(公告)号：US20150116138A1
公开(公告)日：2015-04-30
申请号：US14065732
申请日：2013-10-29
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Zhao Li , David Alldred
IPC: H03M3/00
CPC classification number: H03M3/368 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/38 , H03M3/424 , H03M3/454
Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.
Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。
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Patent Agency Ranking
公开(公告)号：US08912936B1
公开(公告)日：2014-12-16
申请号：US13905251
申请日：2013-05-30
Applicant: Analog Devices Technology
Inventor： Trevor Clifford Caldwell , Richard E. Schreier , David Alldred , Wenhua W. Yang
IPC: H03M3/00
Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.
Abstract translation: 一方面，公开了一种电信号转换器。 示例性电信号转换器可以包括多个有序的转换器元件。 可以提供元素选择逻辑以伪随机选择指向开关矩阵的指针，其中开关矩阵根据逐步的“二进制二最大模式”来映射转换器元件。有利地，可以应用伪随机逐步的Δ-二最大模式 到一阶转换器和用于纠错的反馈转换器。
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4.发明申请SYSTEM, METHOD AND RECORDING MEDIUM FOR ANALOG TO DIGITAL CONVERTER CALIBRATION 有权用于模拟数字转换器校准的系统，方法和记录介质公开(公告)号：US20140266825A1
公开(公告)日：2014-09-18
申请号：US13920083
申请日：2013-06-18
Applicant: Analog Devices Technology
Inventor： Zhao Li , Shipra Bhal , Kevin Glenn Gard , David Alldred , Christopher Mayer , Trevor Clifford Caldwell , David J. McLaurin , Victor Kozlov
IPC: H03M1/10
CPC classification number: H03M3/384 , H03M1/00 , H03M1/1009 , H03M1/12 , H03M3/458
Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.
Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。
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公开(公告)号：US20150171880A1
公开(公告)日：2015-06-18
申请号：US14571274
申请日：2014-12-15
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Trevor Clifford Caldwell , Richard E. Schreier , David Alldred , Wenhua W. Yang
Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.
Abstract translation: 一方面，公开了一种电信号转换器。 示例性电信号转换器可以包括多个有序的转换器元件。 可以提供元素选择逻辑以伪随机选择指向开关矩阵的指针，其中开关矩阵根据逐步的“二进制二最大模式”来映射转换器元件。有利地，可以应用伪随机逐步的Δ-二最大模式 到一阶转换器和用于纠错的反馈转换器。
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公开(公告)号：US20140354459A1
公开(公告)日：2014-12-04
申请号：US13905251
申请日：2013-05-30
Applicant: ANALOG DEVICES TECHNOLOGY
Inventor： Trevor Clifford Caldwell , Richard E. Schreier , David Alldred , Wenhua W. Yang
IPC: H03M3/00
Abstract: In one aspect, an electrical signal converter is disclosed. The exemplary electrical signal converter may include a plurality of ordered converter elements. Element selection logic may be provided to pseudorandomly select a pointer to a switch matrix, wherein the switch matrix maps converter elements according to a stepwise “delta-two-maximum pattern.” Advantageously, pseudorandom stepwise delta-two-maximum patterns may be applied both to a first order converter, and to a feedback converter for error correction.
Abstract translation: 一方面，公开了一种电信号转换器。 示例性电信号转换器可以包括多个有序的转换器元件。 可以提供元素选择逻辑以伪随机选择指向开关矩阵的指针，其中开关矩阵根据逐步的“二进制二最大模式”来映射转换器元件。有利地，可以应用伪随机逐步的Δ-二最大模式 到一阶转换器和用于纠错的反馈转换器。
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7.发明授权System, method and recording medium for analog to digital converter calibration 有权用于模数转换器校准的系统，方法和记录介质公开(公告)号：US08884802B2
公开(公告)日：2014-11-11
申请号：US13920083
申请日：2013-06-18
Applicant: Analog Devices Technology
Inventor： Zhao Li , Shipra Bhal , Kevin Glenn Gard , David Alldred , Christopher Mayer , Trevor Clifford Caldwell , David J. McLaurin , Victor Kozlov
CPC classification number: H03M3/384 , H03M1/00 , H03M1/1009 , H03M1/12 , H03M3/458
Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.
Abstract translation: 用于模数转换器（ADC）的校准系统，内部ADC接收模拟输入并将模拟输入转换为数字多位数据。 该校准系统还包括一个参考混洗电路，它洗牌内部ADC的比较器参考值。 此外，校准系统包括校准电路，校准内部ADC的比较器。 校准系统包括基于数字多位数据测量幅度的数字块。 此外，校准系统包括基于数字块的输出来控制校准电路的校准逻辑。
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