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公开(公告)号：US10884855B1
公开(公告)日：2021-01-05
申请号：US16535115
申请日：2019-08-08
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Yonathan Tate , Michael Tsohar , Naftali Sommer , Eyal Gurgi
IPC: G06F11/10 , G11C29/52 , G11C29/04 , H04L1/00 , H03M13/00 , H03M13/11 , G06F9/30 , G11C11/408 , G11C11/4074 , G11C11/56 , G11C11/409
Abstract: A storage device includes circuitry and memory cells that store data in Np programming levels of threshold voltage values. The circuitry defines NRv threshold-sets, each includes Ns read thresholds that define Ns+1 zones, produces Ns readouts by reading, from a target WL, using the NS read thresholds, a target page that was stored encoded using an Error Correction Code (ECC), and produces a reference readout by reading the target page using optimal read thresholds. The circuitry identifies Np programming levels of memory cells in a neighbor WL for classifying target cells in the target WL into Np·NRv cell-groups. The circuitry calculates, per zone, Np LLR values, for the respective Np programming levels, based on the reference readout, the Ns readouts and the classification, assigns the LLR values to the target cells, and recovers the target page by applying to the assigned LLR values soft decoding for decoding the ECC.
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2.发明授权公开(公告)号：US10936455B2
公开(公告)日：2021-03-02
申请号：US16271907
申请日：2019-02-11
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Eyal Gurgi , Michael Tsohar
IPC: G06F11/20
Abstract: A controller includes an interface and storage circuitry. The interface communicates with a memory that includes memory cells that store data in multiple programming levels, and that are organized in Word Lines (WLs). Each WL connects to one or more cell-groups of the memory cells. The memory cells in some cell-groups suffer from an impairment that has a different severity for reading data units of different bit-significance values. The storage circuitry assigns multiple parity groups to data units stored in cell-groups belonging to consecutive WLs, so that a same parity group is assigned to data units of different bit-significance values in neighboring groups of Nwl consecutive WLs. Upon detecting a failure to access a data unit of a given parity group, due to the impairment, the storage circuitry recovers the data unit using other data units assigned to the given parity group, and that are stored in other cell-groups.
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公开(公告)号：US10755787B2
公开(公告)日：2020-08-25
申请号：US16202127
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Assaf Shappir , Itay Sagron , Meir Dalal
Abstract: A storage device includes storage circuitry and multiple memory cells. The memory cells are organized in multiple memory blocks of a nonvolatile memory. The storage circuitry is configured to define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks, to program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory, to verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully, to check a predefined condition for conditionally performing full verification to the memory block, when the predefined condition is fulfilled, to verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully, and to recover, using the redundancy data, at least part of the data programmed that failed verification.
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4.发明申请公开(公告)号：US20180075926A1
公开(公告)日：2018-03-15
申请号：US15810166
申请日：2017-11-13
Applicant: Apple Inc.
Inventor： Barak Sagiv , Einav Yogev , Eli Yazovitsky , Eyal Gurgi , Roi Solomon
CPC classification number: G11C29/44 , G11C29/028 , G11C29/38
Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.
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Patent Agency Ranking
5.发明授权公开(公告)号：US09847141B1
公开(公告)日：2017-12-19
申请号：US15225863
申请日：2016-08-02
Applicant: APPLE INC.
Inventor： Barak Sagiv , Einav Yogev , Eli Yazovitsky , Eyal Gurgi , Roi Solomon
CPC classification number: G11C29/44 , G11C29/028 , G11C29/38
Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.
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公开(公告)号：US10998920B1
公开(公告)日：2021-05-04
申请号：US16801249
申请日：2020-02-26
Applicant: Apple Inc.
Inventor： Yonathan Tate , Eli Yazovitsky , Michael Tsohar
Abstract: A controller includes an interface and circuitry. The interface is coupled to multiple memory cells. The circuitry stores a code word in a group of the memory cells, reads the code word using different thresholds to produce first and second readouts, and checks whether approximating each of first and second numbers of readout errors based on syndrome weights is valid. In response to determining that only the approximation of the second number of errors is valid, the circuitry produces a combined readout by replacing a portion of the bits in the second readout with corresponding bits of the first readout, calculates an enhanced syndrome weight for the combined readout and estimates the first number of errors based on the enhanced syndrome weight. The circuitry improves readout performance from at least the group of the memory cells using at least one of the estimated first and second numbers of errors.
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7.发明授权公开(公告)号：US10438683B2
公开(公告)日：2019-10-08
申请号：US15810166
申请日：2017-11-13
Applicant: Apple Inc.
Inventor： Barak Sagiv , Einav Yogev , Eli Yazovitsky , Eyal Gurgi , Roi Solomon
Abstract: A storage apparatus includes a plurality of memory cells and storage circuitry. The storage circuitry is configured to store a mapping that maps sets of readout bit-flip counts to respective predefined impairment profiles. The impairment profiles specify two or more severity levels of respective impairment types, including read disturb, retention and endurance. Each of the bit-flip counts includes a one-to-zero error count or a zero-to-one error count. The storage circuitry is configured to read data from a group of the memory cells using given readout parameters, to evaluate an actual set of bit-flip counts corresponding to the read data, to classify the group of the memory cells to a respective impairment profile by mapping the actual set of the bit-flip counts using the mapping, and to adapt the readout parameters based on the impairment profile to which the group of the memory cells was classified.
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8.发明申请公开(公告)号：US20200257598A1
公开(公告)日：2020-08-13
申请号：US16271907
申请日：2019-02-11
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Eyal Gurgi , Michael Tsohar
IPC: G06F11/20
Abstract: A controller includes an interface and storage circuitry. The interface communicates with a memory that includes memory cells that store data in multiple programming levels, and that are organized in Word Lines (WLs). Each WL connects to one or more cell-groups of the memory cells. The memory cells in some cell-groups suffer from an impairment that has a different severity for reading data units of different bit-significance values. The storage circuitry assigns multiple parity groups to data units stored in cell-groups belonging to consecutive WLs, so that a same parity group is assigned to data units of different bit-significance values in neighboring groups of Nwl consecutive WLs. Upon detecting a failure to access a data unit of a given parity group, due to the impairment, the storage circuitry recovers the data unit using other data units assigned to the given parity group, and that are stored in other cell-groups.
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公开(公告)号：US20200005873A1
公开(公告)日：2020-01-02
申请号：US16202127
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Assaf Shappir , Itay Sagron , Meir Dalal
Abstract: A storage device includes storage circuitry and multiple memory cells. The memory cells are organized in multiple memory blocks of a nonvolatile memory. The storage circuitry is configured to define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks, to program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory, to verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully, to check a predefined condition for conditionally performing full verification to the memory block, when the predefined condition is fulfilled, to verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully, and to recover, using the redundancy data, at least part of the data programmed that failed verification.
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