公开(公告)号：US11243560B2

公开(公告)日：2022-02-08

申请号：US17066321

申请日：2020-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F1/12 ,  G06F1/32 ,  G06F1/324

Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).

公开(公告)号：US10719376B2

公开(公告)日：2020-07-21

申请号：US16112383

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F3/00 ,  G06F9/44 ,  G06F9/46 ,  G06F13/00 ,  G06F9/54 ,  G06F15/173 ,  G06F9/38

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

公开(公告)号：US10558580B2

公开(公告)日：2020-02-11

申请号：US15273398

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F12/1009 ,  G06F3/06 ,  G06F8/61 ,  G06F13/42 ,  G06F1/24 ,  G06F12/14

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US20190342225A1

公开(公告)日：2019-11-07

申请号：US15973153

申请日：2018-05-07

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Cahya Adiansyah Masputra

IPC: H04L12/863 ,  H04L12/725

Abstract: Methods and apparatus for non-sequential packet transfer. Prior art multi-processor devices implement a complete network communications stack at each processor. The disclosed embodiments provide techniques for delivering network layer (L3) and/or transport layer (L4) data payloads in the order of receipt, rather than according to the data link layer (L2) order. The described techniques enable e.g., earlier packet delivery. Such design topologies can operate within a substantially smaller memory footprint compared to prior art solutions. As a related benefit, applications that are unaffected by data link layer corruptions can receive data immediately (rather than waiting for the re-transmission of an unrelated L4 data flow) and thus the overall network latency can be greatly reduced and user experience can be improved.

公开(公告)号：US10346226B2

公开(公告)日：2019-07-09

申请号：US15720603

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F13/42 ,  G06F13/16 ,  G06F9/46 ,  G06F9/54 ,  G06F13/362 ,  H04W84/04 ,  H04W72/12

Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

公开(公告)号：US20190034368A1

公开(公告)日：2019-01-31

申请号：US16056374

申请日：2018-08-06

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Vladislav Petkov ,  Radha Kumar Pulyala ,  Saurabh Garg ,  Haining Zhang

IPC: G06F13/28 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

公开(公告)号：US20180129269A1

公开(公告)日：2018-05-10

申请号：US15647063

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/32 ,  G06F9/44

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

公开(公告)号：US20180088660A1

公开(公告)日：2018-03-29

申请号：US15721200

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F1/32 ,  G06F9/44 ,  G06F13/42 ,  G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20170249164A1

公开(公告)日：2017-08-31

申请号：US15273413

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F12/1009 ,  G06F12/14 ,  G06F13/42

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US20160224442A1

公开(公告)日：2016-08-04

申请号：US14870923

申请日：2015-09-30

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F11/20 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F11/2028 ,  G06F13/4022 ,  G06F13/4221 ,  G06F2201/805

Abstract: Methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. The present disclosure provides solutions that preserve error information in the event of a fatal error, coordinate reset conditions between independently operable processors, and implement consistent frameworks for error information recovery across a range of potential fatal errors. In one exemplary embodiment, an applications processor (AP) and baseband processor (BB) implement an abort handler and power down handler sequence which enables error recovery over a wide range of crash scenarios. In one variant, assertion of signals between the AP and the BB enables the AP to reset the BB only after error recovery procedures have successfully completed.

Abstract translation: 用于在两个（或多个）可独立操作的处理器之间控制恢复错误信息的方法和装置。 本公开提供了在致命错误的情况下保留错误信息，在独立可操作的处理器之间协调复位条件并且实现用于在一系列潜在致命错误中进行错误信息恢复的一致框架的解决方案。 在一个示例性实施例中，应用处理器（AP）和基带处理器（BB）实现中止处理器和掉电处理程序序列，其能够在广泛的崩溃情况下进行错误恢复。 在一种变型中，AP和BB之间的信号断言使AP能够在错误恢复过程成功完成后重置BB。