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    Register based SIMD lookup table operations
    1.
    发明授权
    Register based SIMD lookup table operations 有权

    公开(公告)号：US12299445B2

    公开(公告)日：2025-05-13

    申请号：US17833504

    申请日：2022-06-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh ,  Yasuko Eckert ,  Bradford Beckmann ,  Michael Estlick ,  Jay Fleischman

    IPC: G06F9/30

    Abstract: An approach is provided for implementing register based single instruction, multiple data (SIMD) lookup table operations. According to the approach, an instruction set architecture (ISA) can support one or more SIMD instructions that enable vectors or multiple values in source data registers to be processed in parallel using a lookup table or truth table stored in one or more function registers. The SIMD instructions can be flexibly configured to support functions with inputs and outputs of various sizes and data formats. Various approaches are also described for supporting very large lookup tables that span multiple registers.

    Systems and methods for programmed branch predictors
    2.
    发明授权
    Systems and methods for programmed branch predictors 有权

    公开(公告)号：US12217059B1

    公开(公告)日：2025-02-04

    申请号：US18193177

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander Toufic Freij ,  Gabriel H. Loh ,  Onur Kayiran

    IPC: G06F9/38 ,  G06F9/30

    Abstract: The disclosed device a controller that sets an iteration counter for a loop based on an iteration value read from a loop iteration instruction for the loop. The controller also updates the iteration counter based on a number of times a loop heading instruction for the loop is decoded. When the iteration counter reaches an end value, the controller selects a not taken identifier for the loop to be fetched, to avoid a branch misprediction. Various other methods, systems, and computer-readable media are also disclosed.

    COMBINED SPARSE AND BLOCK FLOATING ARITHMETIC
    3.
    发明公开
    COMBINED SPARSE AND BLOCK FLOATING ARITHMETIC 审中-公开

    公开(公告)号：US20240201948A1

    公开(公告)日：2024-06-20

    申请号：US18083273

    申请日：2022-12-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh

    IPC: G06F7/483

    CPC classification number: G06F7/483

    Abstract: A processing device for encoding floating point numbers comprising memory configured to store data comprising the floating point numbers and circuitry. The circuitry is configured to, for a set of the floating point numbers, identify which of the floating point numbers represent a zero value and which of the floating point numbers represent a non-zero value, convert the floating point numbers which represent a non-zero value into a block floating point format value and generate an encoded sparse block floating point format value. The circuitry is also configured to, decode floating point numbers. For an encoded block floating point format value, the circuitry converts the encoded block floating point format value to a set of non-zero floating point numbers based on a sparsity mask previously generated to encode the encoded block floating point format value and generates a non-sparse set of floating point values.

    CACHE FOR STORING REGIONS OF DATA
    9.
    发明申请
    CACHE FOR STORING REGIONS OF DATA 审中-公开

    公开(公告)号：US20200183848A1

    公开(公告)日：2020-06-11

    申请号：US16214363

    申请日：2018-12-10

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gabriel H. Loh

    IPC: G06F12/0877

    Abstract: Systems, apparatuses, and methods for efficiently performing memory accesses in a computing system are disclosed. A computing system includes one or more clients, a communication fabric and a last-level cache implemented with low latency, high bandwidth memory. The cache controller for the last-level cache determines a range of addresses corresponding to a first region of system memory with a copy of data stored in a second region of the last-level cache. The cache controller sends a selected memory access request to system memory when the cache controller determines a request address of the memory access request is not within the range of addresses. The cache controller services the selected memory request by accessing data from the last-level cache when the cache controller determines the request address is within the range of addresses.

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