-
公开(公告)号：US20210192087A1
公开(公告)日：2021-06-24
申请号：US16721895
申请日：2019-12-19
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Guhan Krishnan , Carl K. Wakeland , Saikishore Reddipalli , Philip Ng
Abstract: Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.
-
公开(公告)号：US12174747B2
公开(公告)日：2024-12-24
申请号：US17556617
申请日：2021-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Benjamin Tsien , Chintan S. Patel , Guhan Krishnan , Andrew William Lueck , Sreenath Thangarajan
IPC: G06F12/0897
Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.
-
公开(公告)号：US20230110765A1
公开(公告)日：2023-04-13
申请号：US17889956
申请日：2022-08-17
Applicant: ATI TECHNOLOGIES ULC , ADVANCED MICRO DEVICES, INC.
Inventor： Benjamin Koon Pan CHAN , William Lloyd Atkinson , Tung Chuen Kwong , Guhan Krishnan
Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.
-
公开(公告)号：US09477289B2
公开(公告)日：2016-10-25
申请号：US14225244
申请日：2014-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Ashish Jain , Alexander J. Branover , Guhan Krishnan
IPC: G06F1/32
CPC classification number: G06F1/3225 , G06F1/324 , G06F1/3296 , Y02D10/126
Abstract: A system has a plurality of electronic components including a memory, a PHY coupled to the memory, and one or more other electronic components. Power consumed by the PHY is estimated during operation of the system. Estimating the power consumed by the PHY includes modeling the power consumed by the PHY as a linear function with respect to memory bandwidth. Available power for the PHY is determined based at least in part on the estimated power consumed by the PHY. At least a portion of the available power for the PHY is allocated to at least one of the one or more other components.
Abstract translation: 系统具有包括存储器，耦合到存储器的PHY和一个或多个其它电子部件的多个电子部件。 在系统运行期间估计PHY消耗的功率。 估计PHY消耗的功率包括将PHY消耗的功率建模为相对于存储器带宽的线性函数。 至少部分地基于PHY消耗的估计功率确定PHY的可用功率。 用于PHY的可用功率的至少一部分被分配给一个或多个其它组件中的至少一个。
-
公开(公告)号：US20250004652A1
公开(公告)日：2025-01-02
申请号：US18345927
申请日：2023-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Benjamin Tsien , Chintan S. Patel , Guhan Krishnan
IPC: G06F3/06 , G06F12/0802
Abstract: The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media are also disclosed.
-
Patent Agency Ranking
公开(公告)号：US20230093933A1
公开(公告)日：2023-03-30
申请号：US17500790
申请日：2021-10-13
Applicant: Advanced Micro Devices, Inc.
Inventor： Hui Zhou , Guhan Krishnan , Dong ZhongFei
Abstract: Systems and methods are disclosed that provide low latency augmented reality architecture for camera enabled devices. Systems and methods of communication between system components are presented that use a hybrid communication protocol. Techniques include communications between system components that involve one-way transactions. A hardware message controller is disclosed that controls out-buffers and in-buffers to facilitate the hybrid communication protocol.
-
公开(公告)号：US11514194B2
公开(公告)日：2022-11-29
申请号：US16721895
申请日：2019-12-19
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Guhan Krishnan , Carl K. Wakeland , Saikishore Reddipalli , Philip Ng
Abstract: Devices, methods, and systems for secure communications on a computing device. A host operating system (OS) runs on a host processor in communication with a host memory. A secure OS runs on a coprocessor in communication with a secure memory. The coprocessor receives information from an external device over a secure peer-to-peer (P2P) connection. The secure P2P connection is managed by the secure OS and is not accessible by the host OS.
-
公开(公告)号：US20210191737A1
公开(公告)日：2021-06-24
申请号：US16718656
申请日：2019-12-18
Applicant: Advanced Micro Devices, Inc.
Inventor： Jyoti Raheja , Hideki Kanayama , Guhan Krishnan , Ruihua Peng
IPC: G06F9/4401 , G06F12/0804 , G06F1/3234 , G06F1/3287
Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.
-
公开(公告)号：US11709711B2
公开(公告)日：2023-07-25
申请号：US17120215
申请日：2020-12-13
Applicant: Advanced Micro Devices, Inc.
Inventor： Guhan Krishnan
CPC classification number: G06F9/5016 , G06F9/5022 , G06F13/1668 , G06T1/60
Abstract: An electronic device includes a memory; a plurality of clients; at least one arbiter circuit; and a management circuit. A given client of the plurality of clients communicates a request to the management circuit requesting an allocation of memory access bandwidth for accesses of the memory by the given client. The management circuit then determines, based on the request, a set of memory access bandwidths including a respective memory access bandwidth for each of the given client and other clients of the plurality of clients that are allocated memory access bandwidth. The management circuit next configures the at least one arbiter circuit to use respective memory access bandwidths from the set of memory access bandwidths for the given client and the other clients for subsequent accesses of the memory.
-
公开(公告)号：US20230195644A1
公开(公告)日：2023-06-22
申请号：US17556617
申请日：2021-12-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Benjamin Tsien , Chintan S. Patel , Guhan Krishnan , Andrew William Lueck , Sreenath Thangarajan
IPC: G06F12/0897
CPC classification number: G06F12/0897 , G06F2212/60
Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.017 seconds)
