公开(公告)号：US20210181820A1

公开(公告)日：2021-06-17

申请号：US16717272

申请日：2019-12-17

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sukesh SHENOY ,  Adam N. C. CLARK ,  Christopher M. JAGGERS

IPC: G06F1/20 ,  G01K13/00 ,  G06F1/3287

Abstract: A processing unit manages temperature by correlating readings from a plurality of external temperature sensors to a skin temperature of the processing unit, wherein the correlation is based on characteristics of a computer chassis that is to include the processing unit. The processing unit is mounted on a printed circuit board (PCB) or other substrate that is to be placed in a computer chassis. Each of a plurality of temperature sensors is placed at a different location of the PCB to provide temperature readings from a variety of locations of the PCB. A temperature controller of the processing unit receives temperature readings from the plurality of sensors and correlates the temperature readings with a skin temperature of the processing unit based on a plurality of correlation values.

公开(公告)号：US20240258190A1

公开(公告)日：2024-08-01

申请号：US18102065

申请日：2023-01-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Gamal REFAI-AHMED ,  Chi-Yi CHAO ,  Christopher JAGGERS ,  Suresh RAMALINGAM ,  Sukesh SHENOY

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/40 ,  H01L23/427

CPC classification number: H01L23/3675 ,  H01L21/4817 ,  H01L23/4006 ,  H01L23/427 ,  H01L24/29 ,  H01L24/32 ,  H01L2023/4068 ,  H01L2023/4087 ,  H01L24/16 ,  H01L24/33 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0665

Abstract: A chip package includes a substrate and an integrated circuit (“IC”) die mounted to the substrate. A stiffener frame is mounted to the substrate and circumscribes the IC die. The stiffener frame has a plurality of connected walls that define an opening in the stiffener frame. The chip package also includes a lid having a bottom side facing a top surface of the IC die. The lid has at least a first guide and a second guide extending from the bottom side of the lid. The first guide can be disposed outward or inward of the stiffener frame. The first guide has a side facing an outer wall surface or an inner wall surface of the stiffener frame. The first guide and the second guide are positioned to limit movement of the lid relative to the stiffener frame in two directions.

公开(公告)号：US20250069579A1

公开(公告)日：2025-02-27

申请号：US18236221

申请日：2023-08-21

Applicant: Advanced Micro Devices, Inc. ,  XILINX, INC.

Inventor： Gamal REFAI-AHMED ,  Christopher JAGGERS ,  Hoa DO ,  Md Malekkul ISLAM ,  Paul Theodore ARTMAN ,  Sukesh SHENOY ,  Suresh RAMALINGAM ,  Muhammad Afiq Bin In BAHAROM

IPC: G10K11/178

Abstract: In one example, a micro device includes a housing; a chip package disposed in the housing; a noise producing component coupled to the housing. The micro device also includes a noise reduction system having a reference microphone for detecting a noise from the noise producing component and a controller configured to receive the noise from the reference microphone and generate a masking sound signal in response to the detected noise. A speaker is coupled to the housing for producing a masking sound corresponding to the masking sound signal, whereby the masking sound reduces the noise. In another example, the noise producing component comprises a fan.

公开(公告)号：US20210182066A1

公开(公告)日：2021-06-17

申请号：US16712891

申请日：2019-12-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sukesh SHENOY ,  Adam N. C. CLARK ,  Indrani PAUL

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38 ,  G06F1/3203

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.