公开(公告)号：US12002743B2

公开(公告)日：2024-06-04

申请号：US17402239

申请日：2021-08-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49838

Abstract: An electronic carrier and a method of manufacturing an electronic carrier are provided. The electronic carrier includes a first interconnection structure and a second interconnection structure. The first interconnection structure includes a first patterned conductive layer having a first pattern density. The second interconnection structure is laminated to the first interconnection structure and includes a second patterned conductive layer having a second pattern density higher than the first pattern density. The first interconnection structure is electrically coupled to the second interconnection structure through a first non-soldering joint between and outside of the first interconnection structure and the second interconnection structure.

公开(公告)号：US11705401B2

公开(公告)日：2023-07-18

申请号：US17225832

申请日：2021-04-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4889 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48195 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.

公开(公告)号：US11682656B2

公开(公告)日：2023-06-20

申请号：US17499646

申请日：2021-10-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.

公开(公告)号：US11631633B2

公开(公告)日：2023-04-18

申请号：US17204833

申请日：2021-03-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Kuang-Hsiung Chen ,  Bernd Karl Appelt

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/768 ,  H01L21/50

Abstract: A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.

公开(公告)号：US12002729B2

公开(公告)日：2024-06-04

申请号：US17390697

申请日：2021-07-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589

Abstract: A electronic package and a method of manufacturing the same are provided. The electronic package includes an electronic component, a thermal spreading element, and an encapsulant. The electronic component has a first surface. The thermal spreading element is disposed over the electronic component and has a first surface facing the first surface of the electronic component. The encapsulant covers the electronic component and has a first surface closer to the first surface of the thermal spreading element than the first surface of the electronic component.

公开(公告)号：US11545406B2

公开(公告)日：2023-01-03

申请号：US17066407

申请日：2020-10-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A substrate structure, a semiconductor package structure including the same and a method for manufacturing the same are provided. The substrate structure includes a first passivation layer, a first circuit layer and a first protection layer. The first passivation layer has a first surface and a second surface opposite to the first surface. The first circuit layer has an outer lateral surface. A first portion of the first circuit layer is disposed in the first passivation layer. The first protection layer is disposed on a second portion of the first circuit layer and exposed from the first surface of the first passivation layer. The outer lateral surface of the first circuit layer is covered by the first passivation layer or the first protection layer.

公开(公告)号：US11322468B2

公开(公告)日：2022-05-03

申请号：US16860877

申请日：2020-04-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/00

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad.

公开(公告)号：US11282777B2

公开(公告)日：2022-03-22

申请号：US16732149

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.

公开(公告)号：US11145624B2

公开(公告)日：2021-10-12

申请号：US16523787

申请日：2019-07-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.

公开(公告)号：US20140021636A1

公开(公告)日：2014-01-23

申请号：US14033673

申请日：2013-09-23

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Yuan-Chang Su ,  Shih-Fu Huang ,  Chia-Cheng Chen ,  Tzu-Hui Chen ,  Kuang-Hsiung Chen ,  Pao-Ming Hsieh ,  Ming Chiang Lee ,  Bernd Karl Appelt

IPC: H01L23/522

CPC classification number: H01L24/14 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/28 ,  H01L23/296 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/49155 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

Abstract translation: 多层衬底包括第一外部导电图案化层，暴露第一外部导电图案化层的一部分以限定第一组焊盘的第一绝缘层，第二外部导电图案化层和暴露部分第一绝缘层的第二绝缘层 第二外导电图案层以限定第二组焊盘。 多层基板还包括内层，每层具有内部导电图案层，邻近内部导电图案化层形成的多个内部导电柱和内部电介质层，其中内部导电图案层和内部导电柱嵌入内部 电介质层和每个内部导电柱的顶表面从内部电介质层露出。