公开(公告)号：US11222845B2

公开(公告)日：2022-01-11

申请号：US16593884

申请日：2019-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-I Wu ,  Chen-Chao Wang

IPC: H01L23/52 ,  H01L23/528

Abstract: A semiconductor device includes a dielectric layer, a first conductive layer penetrating the dielectric layer, and a grounding structure disposed within the dielectric layer and adjacent to the first conductive layer. The dielectric layer has a first surface and a second surface opposite the first surface. The first conductive layer has a first portion and a second portion connected to the first portion. The first portion has a width greater than that of the second portion.

公开(公告)号：US10236240B2

公开(公告)日：2019-03-19

申请号：US15152316

申请日：2016-05-11

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yuan-Hsi Chou ,  Tsun-Lung Hsieh ,  Chen-Chao Wang

IPC: H01L23/00 ,  H01L23/498

Abstract: In one or more embodiments, a substrate includes a patterned conductive layer and a reference layer. The patterned conductive layer includes a pair of first conductive traces, a pair of second conductive traces and a reference trace between the pair of first conductive traces and the pair of second conductive traces. The reference layer is above the patterned conductive layer and defines an opening.

公开(公告)号：US20140203412A1

公开(公告)日：2014-07-24

申请号：US13748068

申请日：2013-01-23

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

Abstract translation: 本发明提供半导体晶片，半导体芯片和半导体封装。 半导体晶片包括第一焊盘，第一层间电介质和第二焊盘。 第一焊盘设置在半导体衬底的顶表面上，并且具有实心部分和多个通孔。 第一层间电介质覆盖第一焊盘。 第二焊盘设置在第一层间电介质上，具有实心部分和多个通孔，其中第一焊盘的通孔对应于第二焊盘的实心部分。

公开(公告)号：US11424167B2

公开(公告)日：2022-08-23

申请号：US17067565

申请日：2020-10-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Chih-Yi Huang ,  Keng-Tuan Chang

IPC: H01L21/56 ,  H01L21/66 ,  H01L25/00 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package structure and a method for manufacturing the same are provided. The method includes: providing a package body includes a first semiconductor device, wherein the first semiconductor device includes a plurality of first electrical contacts disposed adjacent to an active surface of the first semiconductor device; measuring the actual positions of the first electrical contacts of the first semiconductor device; providing a plurality of second electrical contacts outside the first semiconductor device; and forming an interconnection structure based on the actual positions of the first electrical contacts of the first semiconductor device and the positions of the second electrical contacts satisfying a predetermined electrical performance criterion by a mask-less process, so as to connect the first electrical contacts and the second electrical contacts and maintain signal integrity during transmission.

公开(公告)号：US11328999B2

公开(公告)日：2022-05-10

申请号：US16706533

申请日：2019-12-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Fu-Chen Chu ,  Hung-Chun Kuo ,  Chen-Chao Wang

IPC: H01L23/538 ,  H01L23/552 ,  H01L23/00

Abstract: A semiconductor device package includes a lower-density substrate and a higher-density substrate. The higher-density substrate is attached to the lower-density substrate. The higher-density substrate has a first interconnection layer and a second interconnection layer disposed over the first interconnection layer. A thickness of the first interconnection layer is different from a thickness of the second interconnection layer.

公开(公告)号：US10276382B2

公开(公告)日：2019-04-30

申请号：US15615665

申请日：2017-06-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard Hunt ,  William T. Chen ,  Chih-Pin Hung ,  Chen-Chao Wang

IPC: H01L21/00 ,  H01L21/108 ,  H01L21/768 ,  H01L23/04 ,  H01L23/48 ,  H01L23/485 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L27/108 ,  H01L23/16 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L23/31

Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.

公开(公告)号：US12216157B2

公开(公告)日：2025-02-04

申请号：US18236930

申请日：2023-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Tsung-Tang Tsai ,  Chih-Yi Huang

IPC: H01L23/498 ,  G01R31/28 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

公开(公告)号：US11232998B2

公开(公告)日：2022-01-25

申请号：US16732054

申请日：2019-12-31

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ming-Fong Jhong ,  Chen-Chao Wang ,  Hung-Chun Kuo

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L21/48 ,  H01L23/528 ,  H01L23/498

Abstract: A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.

公开(公告)号：US10186779B2

公开(公告)日：2019-01-22

申请号：US15348854

申请日：2016-11-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yu Ho ,  Chen-Chao Wang ,  Chun-Yen Ting ,  Ming-Fong Jhong ,  Po-Chih Pan

IPC: H01L23/34 ,  H01Q9/04 ,  H01L23/538 ,  H01L23/552 ,  H01L23/66 ,  H01L25/065 ,  H01Q13/10 ,  H01Q19/30 ,  H01Q21/28 ,  H01L23/00

Abstract: Various embodiments of the present disclosure relate to a semiconductor device package including a carrier, an electrical component, an antenna, a conductive pad and a conductive line. The carrier includes a top surface. The electrical component is disposed over the top surface of the carrier. The antenna is disposed over the top surface of the carrier and spaced away from the electrical component. The conductive pad is disposed over the top surface of the carrier and beneath the antenna, wherein the conductive pad includes a resonant structure. The conductive line is electrically connected to the electrical component and extends within the carrier. A part of the conductive line is beneath the antenna and the resonant structure of the conductive pad.

公开(公告)号：US08841751B2

公开(公告)日：2014-09-23

申请号：US13748068

申请日：2013-01-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chen-Chao Wang ,  Ying-Te Ou

IPC: H01L29/06 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76877 ,  H01L21/302 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49513 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L2224/04026 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83365 ,  H01L2924/00014 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/10158 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.

Abstract translation: 本发明提供半导体晶片，半导体芯片和半导体封装。 半导体晶片包括第一焊盘，第一层间电介质和第二焊盘。 第一焊盘设置在半导体衬底的顶表面上，并且具有实心部分和多个通孔。 第一层间电介质覆盖第一焊盘。 第二焊盘设置在第一层间电介质上，具有实心部分和多个通孔，其中第一焊盘的通孔对应于第二焊盘的实心部分。