公开(公告)号：US20200279814A1

公开(公告)日：2020-09-03

申请号：US16289067

申请日：2019-02-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung HUANG ,  Meng-Kai SHIH ,  Wei-Hong LAI ,  Wei Chu SUN

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L23/552 ,  H01L23/31 ,  H01L21/48 ,  H01L21/66

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

公开(公告)号：US20230011464A1

公开(公告)日：2023-01-12

申请号：US17944114

申请日：2022-09-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Wen Hung HUANG ,  Meng-Kai SHIH ,  Wei-Hong LAI ,  Wei Chu SUN

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/552 ,  H01L21/48 ,  H01L23/498 ,  H01L21/66

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

公开(公告)号：US20160240481A1

公开(公告)日：2016-08-18

申请号：US14624331

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chia-Ching CHEN ,  Chin-Li KAO ,  Hung-Jen CHANG ,  Tang-Yuan CHEN ,  Wei-Hong LAI

IPC: H01L23/538 ,  H05K1/11 ,  H01L21/683 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L2221/68345 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15331 ,  H05K3/205 ,  H05K2201/10378

Abstract: Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.

Abstract translation: 这里描述了用于翘曲控制的插入式衬底设计，包括所述插入器衬底的半导体结构及其制造工艺。 插入器基板限定空腔并且还包括加强结构，其中加强结构用于控制半导体封装结构的翘曲。

公开(公告)号：US20200381345A1

公开(公告)日：2020-12-03

申请号：US16427197

申请日：2019-05-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE ,  Wei-Hong LAI ,  Meng-Kai SHIH

IPC: H01L23/498 ,  H01L25/11 ,  H01L23/31 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device package includes a carrier, a conductive pillar and a first package body. The carrier has a first surface and a second surface opposite to the first surface. The conductive pillar is disposed on the second surface of the carrier. The first package is disposed on the second surface of the carrier and covers at least a portion of the conductive pillar. The conductive pillar has an uneven width.

公开(公告)号：US20180122749A1

公开(公告)日：2018-05-03

申请号：US15340808

申请日：2016-11-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Chih LEE ,  Chin-Cheng KUO ,  Yung-Hui WANG ,  Wei-Hong LAI ,  Chung-Ting WANG ,  Hsiao-Yen LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81192

Abstract: A semiconductor wafer includes a substrate structure, a first insulation layer, a conductive layer and a second insulation layer. The substrate structure defines a via. The first insulation layer covers a surface of the substrate structure. The first insulation layer extends into the via, covers a lateral wall of the via and exposes a bottom surface at a bottom of the via. The conductive layer covers the first insulation layer and the bottom surface exposed by the first insulation layer. The second insulation layer covers the conductive layer. A warpage of the semiconductor wafer is less than 550 micrometers.