公开(公告)号：US12094709B2

公开(公告)日：2024-09-17

申请号：US17390151

申请日：2021-07-30

Applicant: Applied Materials, Inc.

Inventor： Jung Chan Lee ,  Mun Kyu Park ,  Jun Lee ,  Euhngi Lee ,  Kyu-Ha Shim ,  Deven Matthew Raj Mittal ,  Sungho Jo ,  Timothy Miller ,  Jingmei Liang ,  Praket Prakash Jha ,  Sanjay G. Kamath

IPC: H01L21/02

CPC classification number: H01L21/0234 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02271

Abstract: Embodiments of the present disclosure generally relate to methods for gap fill deposition and film densification on microelectronic devices. The method includes forming an oxide layer containing silicon oxide and having an initial wet etch rate (WER) over features disposed on the substrate, and exposing the oxide layer to a first plasma treatment to produce a treated oxide layer. The first plasma treatment includes generating a first plasma by a first RF source and directing the first plasma to the oxide layer by a DC bias. The method also includes exposing the treated oxide layer to a second plasma treatment to produce a densified oxide layer. The second plasma treatment includes generating a second plasma by top and side RF sources and directing the second plasma to the treated oxide layer without a bias. The densified oxide layer has a final WER of less than one-half of the initial WER.

公开(公告)号：US20250037989A1

公开(公告)日：2025-01-30

申请号：US18907769

申请日：2024-10-07

Applicant: Applied Materials, Inc.

Inventor： Ning Li ,  Shuaidi Zhang ,  Mihaela A. Balseanu ,  Qi Gao ,  Rajesh Prasad ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Deven Matthew Raj Mittal ,  Kyu-Ha Shim

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/56 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.

公开(公告)号：US12142475B2

公开(公告)日：2024-11-12

申请号：US17667704

申请日：2022-02-09

Applicant: Applied Materials, Inc.

Inventor： Ning Li ,  Shuaidi Zhang ,  Mihaela A. Balseanu ,  Qi Gao ,  Rajesh Prasad ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Deven Matthew Raj Mittal ,  Kyu-Ha Shim

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/56 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B43/27

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.

公开(公告)号：US20240332009A1

公开(公告)日：2024-10-03

申请号：US18616689

申请日：2024-03-26

Applicant: Applied Materials, Inc.

Inventor： Qixin Shen ,  Chuanxi Yang ,  Hang Yu ,  Deenesh Padhi ,  Prashanthi Para ,  Miguel S. Fung ,  Rajesh Prasad ,  Fenglin Wang ,  Shan Tang ,  Kyu-Ha Shim

IPC: H01L21/02 ,  H01L21/67

CPC classification number: H01L21/02321 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/67213

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon nitride on a semiconductor substrate. The layer of silicon nitride may be characterized by a first roughness. The methods may include performing a post-deposition treatment on the layer of silicon nitride. The methods may include reducing a roughness of the layer of silicon nitride such that the layer of silicon nitride may be characterized by a second roughness less than the first roughness.

公开(公告)号：US11728383B2

公开(公告)日：2023-08-15

申请号：US17032419

申请日：2020-09-25

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Wei Zou ,  Kyu-Ha Shim ,  Qintao Zhang

IPC: H01L29/10 ,  H01L29/76 ,  H01L21/265

CPC classification number: H01L29/1054 ,  H01L21/265 ,  H01L29/7606

Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

公开(公告)号：US20220328337A1

公开(公告)日：2022-10-13

申请号：US17226277

申请日：2021-04-09

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Kyu-Ha Shim

IPC: H01L21/683 ,  C23C14/48 ,  C23C14/06 ,  C23C14/08

Abstract: A method of modifying a high-resistivity substrate so that the substrate may be electrostatically clamped to a chuck is disclosed. The bottom surface is implanted with a resistivity-reducing species. In this way, resistivity of the bottom surface of the substrate may be greatly reduced. In some embodiments, to implant the bottom surface, a coating is applied to the top surface. After application of the coating, the substrate is flipped so that the front surface contacts the top surface of the chuck.
The ions are then implanted into the exposed bottom surface to create the low resistivity layer. The resistivity of the low resistivity layer proximate the bottom surface after implant may be less than 1000 ohm-cm. Once the bottom surface has been implanted, the substrate may be processed conventionally. The low resistivity layer may later be removed by wafer backside thinning processes.

公开(公告)号：US20220102500A1

公开(公告)日：2022-03-31

申请号：US17032419

申请日：2020-09-25

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Wei Zou ,  Kyu-Ha Shim ,  Qintao Zhang

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/76

Abstract: A P-type field effect transistor (PFET) device and a method for fabricating a PFET device using fully depleted silicon on insulator (FDSOI) technology is disclosed. The method includes introducing germanium into the channel layer using ion implantation. This germanium implant increases the axial stress in the channel layer, improving device performance. This implant may be performed at low temperatures to minimize damage to the crystalline structure. Further, rather than using a long duration, high temperature anneal process, the germanium implanted in the channel layer may be annealed using a laser anneal or a rapid temperature anneal. The implanted regions are re-crystallized using the channel layer that is beneath the gate as the seed layer. In some embodiments, an additional oxide spacer is used to further separate the raised source and drain regions from the gate.

公开(公告)号：US11664419B2

公开(公告)日：2023-05-30

申请号：US17065065

申请日：2020-10-07

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Wei Zou ,  Kyu-Ha Shim

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76243

Abstract: A method of isolating sections of the channel layer in a SOI workpiece is disclosed. Rather than etching material to create trenches, which are then filled with a dielectric material, ions are implanted into portions of the channel layer to transform these implanted regions from silicon or silicon germanium into an electrically insulating material. These ions may comprise at least one isolating species, such as oxygen, nitrogen, carbon or boron. This eliminates various processes from the fabrication sequence, including an etching process and a deposition process. Advantageously, this approach also results in greater axial strain in the channel layer, since the channel layer is continuous across the workpiece.

公开(公告)号：US11594441B2

公开(公告)日：2023-02-28

申请号：US17226277

申请日：2021-04-09

Applicant: Applied Materials, Inc.

Inventor： Sipeng Gu ,  Kyu-Ha Shim

IPC: C23C14/00 ,  H01L21/683 ,  C23C14/08 ,  C23C14/06 ,  C23C14/48

Abstract: A method of modifying a high-resistivity substrate so that the substrate may be electrostatically clamped to a chuck is disclosed. The bottom surface is implanted with a resistivity-reducing species. In this way, resistivity of the bottom surface of the substrate may be greatly reduced. In some embodiments, to implant the bottom surface, a coating is applied to the top surface. After application of the coating, the substrate is flipped so that the front surface contacts the top surface of the chuck. The ions are then implanted into the exposed bottom surface to create the low resistivity layer. The resistivity of the low resistivity layer proximate the bottom surface after implant may be less than 1000 ohm-cm. Once the bottom surface has been implanted, the substrate may be processed conventionally. The low resistivity layer may later be removed by wafer backside thinning processes.

公开(公告)号：US20220262619A1

公开(公告)日：2022-08-18

申请号：US17667704

申请日：2022-02-09

Applicant: Applied Materials, Inc.

Inventor： Ning Li ,  Shuaidl Zhang ,  Mihaela A. Balseanu ,  Qi Gao ,  Rajesh Prasad ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Deven Matthew Raj Mittal ,  Kyu-Ha Shim

IPC: H01L21/02

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.