公开(公告)号：US11309406B2

公开(公告)日：2022-04-19

申请号：US16770362

申请日：2018-12-05

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong He ,  Sen Zhang ,  Guangsheng Zhang ,  Yun Lan

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/417 ,  H01L21/033 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

Abstract: A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

公开(公告)号：US10290726B2

公开(公告)日：2019-05-14

申请号：US15548290

申请日：2016-01-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan Gu ,  Wei Su ,  Sen Zhang

IPC: H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/735 ,  H01L29/739

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

公开(公告)号：US12119395B2

公开(公告)日：2024-10-15

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long Zhang ,  Jie Ma ,  Yan Gu ,  Sen Zhang ,  Jing Zhu ,  Jinli Gong ,  Weifeng Sun ,  Longxing Shi

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

公开(公告)号：US11984813B2

公开(公告)日：2024-05-14

申请号：US17435789

申请日：2020-05-15

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shen Xu ,  Siyu Zhao ,  Congming Qi ,  Sen Zhang ,  Xiaoyu Shi ,  Weifeng Sun ,  Longxing Shi

IPC: H02M3/335 ,  H02M1/00 ,  H02M1/38

CPC classification number: H02M3/33592 ,  H02M1/0058 ,  H02M1/38

Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

公开(公告)号：US20210249403A1

公开(公告)日：2021-08-12

申请号：US17267835

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/866

Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

公开(公告)号：US11056402B2

公开(公告)日：2021-07-06

申请号：US16643170

申请日：2018-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Lihui Gu ,  Sen Zhang ,  Congming Qi

IPC: H01L21/8234 ,  H01L29/76 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/739 ,  H01L29/78 ,  H01L27/02

Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS device (N1).

公开(公告)号：US10014392B2

公开(公告)日：2018-07-03

申请号：US15564172

申请日：2016-01-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shukun Qi ,  Guangsheng Zhang ,  Guipeng Sun ,  Sen Zhang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835

Abstract: Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (110), a source (150), a drain (140), a body region (160), a P-type field-limiting ring (135), and a well region on the substrate (110); the well region comprises an inserted well (122), which has P-type doping and is disposed below the drain and connected to the drain; N wells (124) disposed at the two sides of the inserted well (122); a P well (126) disposed next to the N well (124) and connected to the N well (124); a P-type field-limiting ring (135), which is disposed inside the N well (124), is a closed ring-shaped structure, and is located at the periphery below the drain (140); the inserted well (122) extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (135); the source (150) and the body region (160) are disposed inside the P well (126).

公开(公告)号：US12249645B2

公开(公告)日：2025-03-11

申请号：US17620952

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Zhili Zhang ,  Jingchuan Zhao ,  Sen Zhang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method of manufacturing the LDMOS device are disclosed. The method includes: obtaining a substrate with a drift region formed thereon, the drift region having a first conductivity type and disposed on the substrate of a second conductivity type; etching the drift region to form therein a sinking structure, the sinking structure includes at least one of an implanting groove and an implanting hole; implanting ions of the second conductivity type at the bottom of the sinking structure; forming a buried layer of the second conductivity type by causing diffusion of the ions of the second conductivity type using a thermal treatment; and filling an electrical property modification material into the sinking structure, the electrical property modification material differs from the material of the drift region.

公开(公告)号：US11887979B2

公开(公告)日：2024-01-30

申请号：US17267835

申请日：2019-08-15

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang Cheng ,  Yan Gu ,  Sen Zhang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/866

CPC classification number: H01L27/0255 ,  H01L27/0262 ,  H01L27/0296 ,  H01L29/66106 ,  H01L29/866

Abstract: A transient voltage suppression device and a manufacturing method therefor, the transient voltage suppression device including: a substrate, a first conductivity type well region and a second conductivity type well region disposed in the substrate. The first conductivity type well region includes a first well, a second well, and a third well. The second conductivity type well region includes a fourth well that isolates the first well from the second well, and a fifth well that isolates the second well from the third well. The device further includes a Zener diode well region provided in the first well, a first doped region provided in the Zener diode well region, a second doped region provided in the Zener diode well region, a third doped region provided in the second well, a fourth doped region provided in the third well, and a fifth doped region provided in the third well.

公开(公告)号：US11387349B2

公开(公告)日：2022-07-12

申请号：US17265587

申请日：2019-10-14

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan Gu ,  Shikang Cheng ,  Sen Zhang

IPC: H01L29/66 ,  H01L29/78

Abstract: A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.