REDUCING NOISE IN A CAPACITIVE SENSOR WITH A PULSE DENSITY MODULATOR

    公开(公告)号:US20200292602A1

    公开(公告)日:2020-09-17

    申请号:US16890727

    申请日:2020-06-02

    Abstract: A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an intermediate signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, converting the intermediate signal into a pulse-density modulated output signal with a pulse-density modulator, and shaping a noise transfer function of the pulse-density modulator to have an approximate zero at the carrier frequency.

    REDUCING NOISE IN A CAPACITIVE SENSOR WITH A PULSE DENSITY MODULATOR

    公开(公告)号:US20190056440A1

    公开(公告)日:2019-02-21

    申请号:US15926734

    申请日:2018-03-20

    Abstract: A method for measuring a capacitive sensor output may include applying an excitation signal to a capacitor of the capacitive sensor which causes generation of a modulated signal from a baseband signal, wherein the excitation signal is of a carrier frequency which is higher than frequency content of the baseband signal, demodulating the modulated signal to generate an intermediate signal representative of a capacitance of the capacitor wherein the demodulating is based, at least in part, on the excitation signal, converting the intermediate signal into a pulse-density modulated output signal with a pulse-density modulator, and shaping a noise transfer function of the pulse-density modulator to have an approximate zero at the carrier frequency.

    MULTI-CHIP SYNCHRONIZATION IN SENSOR APPLICATIONS

    公开(公告)号:US20240187205A1

    公开(公告)日:2024-06-06

    申请号:US18471856

    申请日:2023-09-21

    CPC classification number: H04L7/033 H04J3/0688

    Abstract: A system may include a plurality of devices coupled to one another via a shared digital wired communication link, the plurality of devices comprising a first device configured to periodically transmit a synchronization packet onto the shared digital wired communication link to synchronize other of the plurality of devices to a reference clock of the first device, a second device configured to receive the synchronization packet and transmit one or more first data packets onto the shared digital wired communication link in response to the synchronization packet, and a third device configured to receive the synchronization packet and transmit one or more second data packets onto the shared digital wired communication link in response to the synchronization packet and the one or more second data packets.

    TRACKING AND CORRECTING GAIN OF OPEN-LOOP DRIVER IN A MULTI-PATH PROCESSING SYSTEM

    公开(公告)号:US20200228079A1

    公开(公告)日:2020-07-16

    申请号:US16828401

    申请日:2020-03-24

    Abstract: A multi-path subsystem may include a first processing path, a second processing path, a mixed signal return path, and a calibration engine configured to: estimate and cancel a direct current (DC) offset of the mixed signal return path, estimate and cancel a DC offset between the first processing path and the second processing path, estimate and cancel a phase difference between the first processing path and a sum of the second processing path and the mixed signal return path, estimate and cancel a return path gain of the mixed signal return path, and track and correct for a gain difference between the first processing path and the second processing path.

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