公开(公告)号：US5929481A

公开(公告)日：1999-07-27

申请号：US964419

申请日：1997-11-04

申请人： Fwu-Iuan Hshieh ,  Brian H. Floyd ,  Mike F. Chang ,  Danny Nim ,  Daniel Ng

发明人： Fwu-Iuan Hshieh ,  Brian H. Floyd ,  Mike F. Chang ,  Danny Nim ,  Daniel Ng

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/1095 ,  H01L29/0878 ,  H01L29/7813

摘要： A trenched DMOS transistor overcomes the problem of a parasitic JFET at the trench bottom (caused by deep body regions extending deeper than the trench) by providing a doped trench bottom implant region at the bottom of the trench and extending into the surrounding drift region. This trench bottom implant region has the same doping type, but is more highly doped, than the surrounding drift region. The trench bottom implant region significantly reduces the parasitic JFET resistance by optimizing the trench bottom implant dose, without creating reliability problems.

摘要翻译： 沟槽DMOS晶体管通过在沟槽的底部提供掺杂的沟槽底部注入区域并延伸到周围的漂移区域来克服沟槽底部的寄生JFET（由深沟槽深度延伸的深度）引起的问题。 该沟槽底部注入区域具有与周围漂移区域相同的掺杂类型，但是掺杂度更高。 通过优化沟槽底部注入剂量，沟槽底部注入区域显着降低寄生JFET电阻，而不会产生可靠性问题。

公开(公告)号：US06444527B1

公开(公告)日：2002-09-03

申请号：US09481135

申请日：2000-01-11

申请人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L21336

CPC分类号： H01L29/7811 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/7722 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827

摘要： A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

摘要翻译： 适合于低电压功率应用的沟槽场效应晶体管由于源极区和漏极区之间的栅极控制势垒区而提供低泄漏阻挡能力。 通过源极区域和漏极区域之间的反转区域发生正向导通。 封闭通过栅极控制的耗尽屏障实现。 位于源极和漏极区之间是相当轻掺杂的体区。 位于沟槽中的栅电极延伸穿过源极和体区，并且在一些情况下延伸到漏极区的上部。 多晶硅栅电极的掺杂剂类型与体区相同。 体区是在相对导电类型的高掺杂低电阻率衬底上生长的相对薄且轻掺杂的外延层。 在阻塞状态下，外延体区域由于施加的漏极 - 源极电压而耗尽，因此穿通型状态垂直发生。 横向栅极控制增加了大多数载流子的有效屏障，并将泄漏电流降低到可接受的低水平。

公开(公告)号：US6069043A

公开(公告)日：2000-05-30

申请号：US962885

申请日：1997-11-12

申请人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L29/7722 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0847

摘要： A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

摘要翻译： 适合于低电压功率应用的沟槽场效应晶体管由于源极区和漏极区之间的栅极控制势垒区而提供低泄漏阻挡能力。 通过源极区域和漏极区域之间的反转区域发生正向导通。 封闭通过栅极控制的耗尽屏障实现。 位于源极和漏极区之间是相当轻掺杂的体区。 位于沟槽中的栅电极延伸穿过源极和体区，并且在一些情况下延伸到漏极区的上部。 多晶硅栅电极的掺杂剂类型与体区相同。 体区是在相对导电类型的高掺杂低电阻率衬底上生长的相对薄且轻掺杂的外延层。 在阻塞状态下，外延体区域由于施加的漏极 - 源极电压而耗尽，因此穿通型状态垂直发生。 横向栅极控制增加了大多数载流子的有效屏障，并将泄漏电流降低到可接受的低水平。

公开(公告)号：US5917216A

公开(公告)日：1999-06-29

申请号：US742326

申请日：1996-10-31

申请人： Brian H. Floyd ,  Dorman C. Pitzer ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Dorman C. Pitzer ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/7827 ,  H01L29/7828 ,  H01L29/0619 ,  H01L29/1033 ,  H01L29/7832

摘要： A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.

摘要翻译： 其导通状态的沟槽MOSFET导通电流通过积聚区域并且穿过沿着沟槽侧壁设置的反向耗尽势垒层。 通过相邻区域的栅极控制耗尽和从沟槽侧壁横向延伸到其中的耗尽阻挡层（具有在截面图中的“耳朵”并且与相邻区域相反的掺杂类型）的外观来实现阻塞。 漂移区。 该MOSFET具有优于现有技术的沟槽MOSFET的导通电阻率，并且在导通状态电阻方面具有良好的性能，同时具有优于现有技术的沟槽MOSFET的阻塞特性。 阻挡特性的改善由作为半导体掺杂区域的耗尽阻挡层提供。 在阻挡状态下，耗尽阻挡层完全或几乎完全耗尽，以防止寄生双极导电。 可以改变耗尽阻挡层的形状和程度，并且可能存在多于一个的耗尽阻挡层。

公开(公告)号：US5592005A

公开(公告)日：1997-01-07

申请号：US415009

申请日：1995-03-31

申请人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

发明人： Brian H. Floyd ,  Fwu-Iuan Hshieh ,  Mike F. Chang

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/772 ,  H01L29/78

CPC分类号： H01L29/7722 ,  H01L29/402 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/0847

摘要： A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

摘要翻译： 适合于低电压功率应用的沟槽场效应晶体管由于源极区和漏极区之间的栅极控制势垒区而提供低泄漏阻挡能力。 通过源极区域和漏极区域之间的反转区域发生正向导通。 封闭通过栅极控制的耗尽屏障实现。 位于源极和漏极区之间是相当轻掺杂的体区。 位于沟槽中的栅电极延伸穿过源极和体区，并且在一些情况下延伸到漏极区的上部。 多晶硅栅电极的掺杂剂类型与体区相同。 体区是在相对导电类型的高掺杂低电阻率衬底上生长的相对薄且轻掺杂的外延层。 在阻塞状态下，外延体区域由于施加的漏极 - 源极电压而耗尽，因此穿通型状态垂直发生。 横向栅极控制增加了大多数载流子的有效屏障，并将泄漏电流降低到可接受的低水平。

公开(公告)号：US6090716A

公开(公告)日：2000-07-18

申请号：US767708

申请日：1996-12-17

申请人： Brian H. Floyd ,  Chin H. Ho ,  Mike F. Chang ,  Min Juang ,  Brian Cheung ,  Karen Lee

发明人： Brian H. Floyd ,  Chin H. Ho ,  Mike F. Chang ,  Min Juang ,  Brian Cheung ,  Karen Lee

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/311

CPC分类号： H01L29/7827

摘要： In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of mesas.An oxide layer of generally uniform thickness is provided over the mesas and in the trenches, and a polysilicon layer is provided over the oxide layer and is etched so that the oxide layer overlying the mesas is exposed, and the top surface of the polysilicon within the trenches is below the level of the tops of the mesas.A layer of spin-on-glass (SOG) is provided, and the SOG layer and oxide layer are etched substantially to the level of the tops of the mesas, to expose the tops of the mesas and to leave the portions of the SOG over the respective polysilicon portions in the trenches substantially coplaner with the tops of the mesas.A conductive layer is provided over the remaining portions of the SOG layer and the tops of the mesas.

摘要翻译： 在本方法中，在半导体衬底上设置有外延层。 源极/漏极区域设置在外延层的一部分中，并且在外延层中蚀刻多个沟槽并延伸到衬底中以限定多个台面。 在台面和沟槽中设置大致均匀厚度的氧化物层，并且在氧化物层上方设置多晶硅层，并且被蚀刻，使得覆盖在台面上的氧化物层被暴露，并且多晶硅的顶表面在 沟渠低于台面顶部的水平。 提供了一层旋涂玻璃（SOG），SOG层和氧化物层被基本蚀刻到台面顶部的水平面，露出台面的顶部，并使SOG的部分过去 沟槽中的各个多晶硅部分与台面的顶部基本上共面。 导电层设置在SOG层的剩余部分和台面的顶部之上。

公开(公告)号：US5998834A

公开(公告)日：1999-12-07

申请号：US651232

申请日：1996-05-22

申请人： Richard K. Williams ,  Brian H. Floyd ,  Wayne Grabowski ,  Mohamed Darwish ,  Mike F. Chang

发明人： Richard K. Williams ,  Brian H. Floyd ,  Wayne Grabowski ,  Mohamed Darwish ,  Mike F. Chang

IPC分类号： H01L27/04 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/1095 ,  H01L29/7813

摘要： A trenched-gate power MOSFET includes a body region that is formed within a mesa between adjacent gate trenches. The doping concentration of the body region is established such that the body region does not fully deplete at normal drain voltages. The MOSFET also includes a gate which is doped with material of a conductivity type opposite to that of the body. The width of the mesa and the doping concentration of the body region and gate are established such that the body region is fully depleted by the combined effects of the source-body and drain body junctions and the gate. As a result, the conventional source-body short can be eliminated, providing a greater cell packing density and lower on-resistance while maintaining acceptable levels of leakage current when the MOSFET is in the off-state.

摘要翻译： 沟槽栅极功率MOSFET包括形成在相邻栅极沟槽之间的台面内的主体区域。 身体区域的掺杂浓度被建立为使得身体区域在正常漏极电压下不完全消耗。 MOSFET还包括掺杂有与体的导电类型相反的导电类型的材料的栅极。 建立台面的宽度和体区域和栅极的掺杂浓度，使得体区域被源体和漏体结与栅极的组合效应完全耗尽。 结果，可以消除传统的源体短路，提供更大的电池堆积密度和更低的导通电阻，同时在MOSFET处于断开状态时保持可接受的漏电流水平。

公开(公告)号：US20090161725A1

公开(公告)日：2009-06-25

申请号：US12004279

申请日：2007-12-19

申请人： Brian H. Floyd

发明人： Brian H. Floyd

IPC分类号： G01K7/00

CPC分类号： G01K7/015

摘要： In one embodiment, an integrated circuit is provided for detecting when a temperature reaches a specified value. The circuit includes a differential circuit block having first and second transistors. A control terminal of the first transistor is coupled to a first voltage source, and a control terminal of the second transistor is coupled to a second voltage source. The second transistor has an area larger than the first transistor. The differential circuit block compares a first current flowing into the first transistor and a second current flowing into the second transistor. The differential circuit block outputs a signal to indicate that the specified temperature has been reached when the first current equals the second current according to specified values of the first voltage source, the second voltage source, and the ratio of the areas of the first and second transistors. A single-ended circuit block amplifies the output signal of the differential circuit block to a predetermined amplitude.

摘要翻译： 在一个实施例中，提供了用于检测何时温度达到指定值的集成电路。 该电路包括具有第一和第二晶体管的差分电路块。 第一晶体管的控制端子耦合到第一电压源，并且第二晶体管的控制端耦合到第二电压源。 第二晶体管的面积大于第一晶体管。 差分电路块比较流入第一晶体管的第一电流和流入第二晶体管的第二电流。 差分电路块根据第一电压源，第二电压源和第一和第二电压源的面积的比值，输出信号以指示当第一电流等于第二电流时达到指定温度 晶体管。 单端电路块将差分电路块的输出信号放大到预定的幅度。

公开(公告)号：US06285177B1

公开(公告)日：2001-09-04

申请号：US09566857

申请日：2000-05-08

申请人： Shekar Mallikarjunaswamy ,  Brian H. Floyd

发明人： Shekar Mallikarjunaswamy ,  Brian H. Floyd

IPC分类号： G05F320

CPC分类号： H03K17/0822 ,  G05F3/262

摘要： A current-limit circuit and a method of limiting current supplied to a load through a power transistor utilize a control transistor that is selectively activated to a conducting state to limit the current conducted through the power transistor in response to a predefined condition. The predefined condition may be a short-circuit condition or an over-current condition. The configuration and operation of the control transistor are such that, when the control transistor is in a conducting state, the current conducted through the power transistor is limited by the structural ratio of the two transistors. However, during normal operating conditions when the control transistor is deactivated to a non-conducting state, the control transistor does not degrade the performance of the power transistor. In a first embodiment, the current-limit circuit is configured to provide protection from a short-circuit condition. In a second embodiment, the current-limit circuit is configured to provide protection from an over-current condition, in addition to protection from a short-circuit condition. In a preferred embodiment, the sense transistor and the power transistor are structurally integrated into a single semiconductor device having a honeycomb structure that allows the size of the sense transistor to be tuned.

摘要翻译： 限流电路和限制通过功率晶体管提供给负载的电流的方法利用控制晶体管，该控制晶体管被选择性地激活到导通状态，以便响应于预定条件来限制传导通过功率晶体管的电流。 预定义的条件可以是短路状态或过电流状态。 控制晶体管的配置和操作使得当控制晶体管处于导通状态时，通过功率晶体管传导的电流受到两个晶体管的结构比的限制。 然而，在正常操作条件下，当控制晶体管被去激活至非导通状态时，控制晶体管不会降低功率晶体管的性能。 在第一实施例中，限流电路被配置为提供防止短路状况的保护。 在第二实施例中，除了防止短路状况外，限流电路被配置为提供防止过电流状态的保护。 在优选实施例中，感测晶体管和功率晶体管在结构上集成到具有允许感测晶体管的尺寸被调谐的蜂窝结构的单个半导体器件中。

公开(公告)号：US07595683B1

公开(公告)日：2009-09-29

申请号：US11985457

申请日：2007-11-15

申请人： Brian H. Floyd

发明人： Brian H. Floyd

IPC分类号： G05F1/10

CPC分类号： H02M3/073

摘要： In one embodiment, a charge pump system includes an input terminal at which an input voltage is received, and an output terminal at which at an output voltage is provided. N stages are connected in cascade between the input terminal and the output terminal. Each of the N stages includes at most one inverter circuit, the inverter circuit having a first transistor connected at a node to a second transistor. A first capacitor is coupled at one end to the node between the first and second transistors, and is coupled at another end to receive one of two non-overlapping phase signals. In each stage, at one value for the one of two non-overlapping phase signals, the first capacitor of the stage is charged by a respective stage input voltage, and at another value for the one of two non-overlapping phase signals the first capacitor of the stage is discharged to provide a respective stage output voltage. The charge pump system is capable of generating the output voltage with a greater magnitude than the input voltage even when the supply voltage is relatively low, e.g., below 1V.

摘要翻译： 在一个实施例中，电荷泵系统包括接收输入电压的输入端子和设置有输出电压的输出端子。 N级在输入端子和输出端子之间级联连接。 N个级中的每一个包括至多一个逆变器电路，所述逆变器电路具有连接到第二晶体管的节点处的第一晶体管。 第一电容器在一端耦合到第一和第二晶体管之间的节点，并且在另一端耦合以接收两个非重叠相位信号中的一个。 在每个阶段中，对于两个非重叠相位信号之一的一个值，级的第一电容器由相应的级输入电压充电，并且在两个非重叠相位信号中的一个的另一个值处，第一电容器 的级放电以提供相应的级输出电压。 即使当电源电压相对较低（例如低于1V）时，电荷泵系统能够产生具有比输入电压更大的幅度的输出电压。