公开(公告)号：US06239463B1

公开(公告)日：2001-05-29

申请号：US08919386

申请日：1997-08-28

申请人： Richard K. Williams ,  Mohamed Darwish ,  Wayne Grabowski ,  Michael E. Cornell

发明人： Richard K. Williams ,  Mohamed Darwish ,  Wayne Grabowski ,  Michael E. Cornell

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/7378 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7802 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7835 ,  H01L29/872

摘要： A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.

摘要翻译： 功率MOSFET或其他半导体器件包含与锗结合的硅层以降低器件的导通电阻。 该层中锗的比例通常在1-40％的范围内。 为了实现所需的特性，Si-Ge层中锗的浓度可以是均匀的，阶梯式的或分级的。 在许多实施例中，期望将锗保持在半导体材料的表面以下以防止锗原子被引入到栅极氧化物层中。 该技术可用于垂直DMOS和沟槽门控MOSFET，准垂直MOSFET和横向MOSFET，以及绝缘栅双极晶体管，晶闸管，肖特基二极管和常规双极晶体管。

公开(公告)号：US07052963B2

公开(公告)日：2006-05-30

申请号：US10767030

申请日：2004-01-28

申请人： Richard K. Williams ,  Wayne Grabowski

发明人： Richard K. Williams ,  Wayne Grabowski

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7808 ,  H01L29/7811

摘要： A “chained implant” technique forms a body region in a trench gated transistor. In one embodiment, a succession of “chained” implants can be performed at the same dose but different energies. In other embodiments different doses and energies can be used, and particularly, more than one dose can be used in a single device. This process produces a uniform body doping concentration and a steeper concentration gradient (at the body-drain junction), with a higher total body charge for a given threshold voltage, thereby reducing the vulnerability of the device to punchthrough breakdown. Additionally, the source-body junction does not, to a first order, affect the threshold voltage of the device, as it does in DMOS devices formed with conventional diffused body processes.

摘要翻译： “链式注入”技术在沟槽门控晶体管中形成体区。 在一个实施例中，可以以相同剂量但不同能量执行一系列“链式”植入物。 在其它实施方案中，可以使用不同的剂量和能量，并且特别地，可以在单个装置中使用多于一个剂量。 该过程产生均匀的体内掺杂浓度和更陡峭的浓度梯度（在体 - 排出结处），对于给定的阈值电压具有较高的总体电荷，从而降低器件穿透击穿的脆弱性。 另外，源 - 体结不一定影响器件的阈值电压，就像在常规扩散体工艺形成的DMOS器件中一样。

公开(公告)号：US6072216A

公开(公告)日：2000-06-06

申请号：US71729

申请日：1998-05-01

申请人： Richard K. Williams ,  Wayne Grabowski

发明人： Richard K. Williams ,  Wayne Grabowski

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66712 ,  H01L21/266 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/42368 ,  Y10S438/981

摘要： A vertical DMOSFET includes a buried layer which is of the same conductivity type as the drain and which extends into the heavily doped substrate and approaches or extends to the surface of the epitaxial layer at a central location in the MOSFET cell that is defined by the body regions of the MOSFET. In some embodiments the upper boundary of the buried layer generally conforms to the shape of the body region, forming a dish shaped structure under the body region. A significant portion of the current flowing through the channel is drawn into the buried layer and since the buried layer represents a relatively low-resistance path, the total resistance of the MOSFET is lowered without any significant effect on the breakdown voltage. The conformal buried layer can be formed by implanting dopant into the epitaxial layer at a high energy (0.5 to 3 MeV). Before the implant, a thick oxide layer is formed in a central region of the MOSFET cell. The dopant penetrates less deeply into the epitaxial layer under the thick oxide layer, and this yields the "conformal" shape of the buried layer. Alternatively, the buried layer can be formed with two implants, i.e., by forming a horizontal buried layer in the epitaxial layer by a blanket implant and by forming a "plug" by implanting through an opening in a mask layer at the center of the cell, the plug overlapping the horizontal layer.

摘要翻译： 垂直DMOSFET包括与漏极具有相同导电类型并且延伸到重掺杂衬底中的掩埋层，并且在由壳体限定的MOSFET电池的中心位置处接近或延伸到外延层的表面 MOSFET的区域。 在一些实施例中，掩埋层的上边界通常符合身体区域的形状，在身体区域下形成碟形结构。 流过沟道的电流的重要部分被吸入埋层，并且由于掩埋层表示相对低电阻的路径，所以MOSFET的总电阻降低，而对击穿电压没有明显的影响。 可以通过以高能量（0.5-3MeV）将掺杂剂注入到外延层中来形成共形掩埋层。 在注入之前，在MOSFET单元的中心区域形成厚的氧化物层。 掺杂剂在较厚的氧化物层下深入到外延层中，这就产生了埋层的“保形”形状。 或者，掩埋层可以形成有两个植入物，即通过在橡皮布植入物在外延层中形成水平掩埋层，并且通过在细胞的中心通过掩模层中的开口注入形成“插塞” ，插头与水平层重叠。

公开(公告)号：US6049108A

公开(公告)日：2000-04-11

申请号：US920330

申请日：1997-08-28

申请人： Richard K. Williams ,  Wayne Grabowski ,  Mohamed Darwish ,  Jacek Korec

发明人： Richard K. Williams ,  Wayne Grabowski ,  Mohamed Darwish ,  Jacek Korec

IPC分类号： H01L21/336 ,  H01L27/02 ,  H01L27/04 ,  H01L27/095 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/872 ,  H01L27/088 ,  H01L29/47

CPC分类号： H01L29/7808 ,  H01L27/0255 ,  H01L27/095 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/872 ,  H01L29/0696

摘要： The gate of a MOSFET is located in a lattice of trenches which define a plurality of cells. Most of the cells contain a MOSFET, but a selected number of the cells at predetermined locations in the lattice contain either a PN diode or a Schottky diode. The PN and Schottky diodes are connected in parallel with the channels in the MOSFET cells, with their anodes tied to the anode of the parasitic diodes in the MOSFET cells and their cathodes tied to the cathode of the parasitic diodes. When the MOSFET is biased in the normal direction (with the parasitic diode reverse-biased), the PN diodes provide a predictable breakdown voltage for the device and ensure that avalanche breakdown occurs at a location away from the trench gate where the hot carriers generated by the breakdown cannot damage the oxide layer which lines the walls of the trench. When the device is biased in the opposite direction, the Schottky diodes conduct and thereby limit charge storage at the PN junctions in the diode and MOSFET cells. This reduces the power loss in the MOSFET and improves the reverse recovery characteristics of the device when its bias is switched back to the normal direction.

摘要翻译： MOSFET的栅极位于限定多个单元的沟槽的格子中。 大多数单元包含MOSFET，但在晶格中预定位置处的选定数量的单元格包含PN二极管或肖特基二极管。 PN和肖特基二极管与MOSFET单元中的通道并联连接，其阳极连接到MOSFET单元中的寄生二极管的阳极，其阴极连接到寄生二极管的阴极。 当MOSFET在正常方向上偏置（寄生二极管反向偏置）时，PN二极管为器件提供可预测的击穿电压，并确保在远离沟槽栅极的位置发生雪崩击穿，其中热载流子由 击穿不能损伤沟槽壁的氧化层。 当器件偏向相反方向时，肖特基二极管导通，从而限制二极管和MOSFET单元PN结处的电荷存储。 这降低了MOSFET中的功率损耗，并且当其偏压切换回法线方向时，可以提高器件的反向恢复特性。

公开(公告)号：US6046470A

公开(公告)日：2000-04-04

申请号：US946613

申请日：1997-10-07

申请人： Richard K. Williams ,  Wayne Grabowski

发明人： Richard K. Williams ,  Wayne Grabowski

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/7813 ,  H01L27/0248 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464

摘要： A vertical N-channel trenched-gate power MOSFET includes an integral temperature detection diode. The diode includes an N+ region which serves as the cathode and which is formed within a tub of P-type material, which serves as the anode. The N+ region is separated from the trench. The anode of the temperature detection diode may be shorted to the source or may be separately biased. The temperature of the MOSFET is monitored by supplying a current through the diode in the forward direction and measuring the voltage across the forward-biased diode. In an alternative embodiment, a pair of N+ regions are formed within the P-tub, constituting a diode pair, and the temperature is detected by monitoring the difference in the voltages across the diodes. An overtemperature detection unit compares the voltage across the diode or diodes with a reference voltage and provides an output which can be used to turn the MOSFET off when the temperature reaches a predetermined level.

摘要翻译： 垂直N沟道沟槽功率MOSFET包括积分温度检测二极管。 二极管包括用作阴极并形成在用作阳极的P型材料的桶内的N +区域。 N +区域与沟槽分离。 温度检测二极管的阳极可能短路到源极，或者可以单独偏置。 通过在正向上提供通过二极管的电流并测量正向偏置二极管两端的电压来监测MOSFET的温度。 在替代实施例中，在P盆内形成一对N +区，构成二极管对，并通过监测二极管两端的电压差来检测温度。 过温检测单元将二极管或二极管两端的电压与参考电压进行比较，并提供可在温度达到预定水平时将MOSFET关断的输出。

公开(公告)号：US06756274B2

公开(公告)日：2004-06-29

申请号：US10146568

申请日：2002-05-14

申请人： Richard K. Williams ,  Wayne Grabowski

发明人： Richard K. Williams ,  Wayne Grabowski

IPC分类号： H01L21336

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7808 ,  H01L29/7811

摘要： A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

摘要翻译： 超自对准（SSA）结构和制造工艺使用单个光掩模层来定义沟槽门垂直功率DMOSFET的关键特征和尺寸。 单个关键掩模确定沟槽表面尺寸，沟槽之间的硅源体台面宽度以及硅台面接触的尺寸和位置。 接触件与沟槽自对准，消除了在传统沟槽DMOS器件中接触沟槽掩模对准所造成的限制，以避免工艺引起的栅极至源极短路。 硅表面上方的氧化物台阶高度也减少，避免了金属台阶覆盖问题。 多门总线步高也减少了。 所描述的其它特征包括多晶硅二极管形成，控制漏极体二极管击穿的位置，减少栅 - 漏重叠电容，以及利用低热预算处理技术。

公开(公告)号：US06750507B2

公开(公告)日：2004-06-15

申请号：US10146668

申请日：2002-05-14

申请人： Richard K. Williams ,  Wayne Grabowski

发明人： Richard K. Williams ,  Wayne Grabowski

IPC分类号： H01L218222

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7808 ,  H01L29/7811

摘要： A super-self-aligned (SSA) structure and manufacturing process uses a single photomasking layer to define critical features and dimensions of a trench-gated vertical power DMOSFET. The single critical mask determines the trench surface dimension, the silicon source-body mesa width between trenches, and the dimensions and location of the silicon mesa contact. The contact is self-aligned to the trench, eliminating the limitation imposed by contact-to-trench mask alignment in conventional trench DMOS devices needed to avoid process-induced gate-to-source shorts. Oxide step height above the silicon surface is also reduced avoiding metal step coverage problems. Poly gate bus step height is also reduced. Other features described include polysilicon diode formation, controlling the location of drain-body diode breakdown, reducing gate-to-drain overlap capacitance, and utilizing low-thermal budget processing techniques.

摘要翻译： 超自对准（SSA）结构和制造工艺使用单个光掩模层来定义沟槽门垂直功率DMOSFET的关键特征和尺寸。 单个关键掩模确定沟槽表面尺寸，沟槽之间的硅源体台面宽度以及硅台面接触的尺寸和位置。 接触件与沟槽自对准，消除了在传统沟槽DMOS器件中接触沟槽掩模对准所造成的限制，以避免工艺引起的栅极至源极短路。 硅表面上方的氧化物台阶高度也减少，避免了金属台阶覆盖问题。 多门总线步高也减少了。 所描述的其它特征包括多晶硅二极管形成，控制漏极体二极管击穿的位置，减少栅 - 漏重叠电容，以及利用低热预算处理技术。

公开(公告)号：US20050215013A1

公开(公告)日：2005-09-29

申请号：US11137151

申请日：2005-05-25

申请人： Richard Williams ,  Wayne Grabowski

发明人： Richard Williams ,  Wayne Grabowski

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8242 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

摘要翻译： 诸如功率MOSFET的沟槽半导体器件通过增加沟槽底部的栅极氧化物层的厚度来减小沟槽拐角处的高电场。 描述了用于制造这种设备的几个过程。 在一组工艺中，在蚀刻沟槽之后进行氧化硅的定向沉积，在沟槽的底部产生厚的氧化物层。 沉积在沟槽壁上的任何氧化物在薄的栅极氧化物层生长在壁上之前被去除。 然后在多层或多层中填充沟槽。 在该方法的变化中，在蚀刻沟槽的壁之前，在沟槽底部的氧化物上沉积少量的光致抗蚀剂。 或者，多晶硅可以沉积在沟槽中并被回蚀，直到只有一部分保留在沟槽的底部。 然后将多晶硅氧化，并用多晶硅再填充沟槽。 该方法可以组合，随着氧化物的定向沉积，随后是多晶硅的填充和氧化。 形成“键孔”形栅电极的工艺包括在沟槽的底部沉积多晶硅，氧化多晶硅的顶表面，蚀刻氧化的多晶硅，并用多晶硅填充沟槽。

公开(公告)号：US20050215012A1

公开(公告)日：2005-09-29

申请号：US11137001

申请日：2005-05-25

申请人： Richard Williams ,  Wayne Grabowski

发明人： Richard Williams ,  Wayne Grabowski

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/8242 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/8083

摘要： The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

公开(公告)号：US06924198B2

公开(公告)日：2005-08-02

申请号：US10767028

申请日：2004-01-28

申请人： Richard K. Williams ,  Wayne Grabowski

发明人： Richard K. Williams ,  Wayne Grabowski

IPC分类号： H01L29/41 ,  H01L21/336 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/739 ,  H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/7808 ,  H01L29/7811

摘要： A trench-gated MOSFET formed using a super self aligned (SSA) process employs an insulating layer such as a glass layer and a contact mask to define contact openings for electrical connections to source regions of the MOSFET. Use a contact mask and an intervening glass in otherwise self-aligned process reduces the coupling capacitance between source metal and the top of the embedded trench gate. A metal layer deposited to make electrical contact to source regions can be planarized, for example, ground flat using chemical-mechanical polishing to provide a flat surface to avoid formation of conductive traces that extend over the steps that the glass layer forms.

摘要翻译： 使用超自对准（SSA）工艺形成的沟槽栅MOSFET采用诸如玻璃层和接触掩模的绝缘层来限定用于与MOSFET的源极区域的电连接的接触开口。 使用接触掩模和中间玻璃，否则自对准过程会降低源极金属与嵌入式沟槽栅极顶部之间的耦合电容。 沉积以与源区电接触的金属层可以被平坦化，例如，使用化学 - 机械抛光来研磨平坦化以提供平坦表面，以避免在玻璃层形成的台阶上延伸的导电迹线的形成。