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    Transistors patterned with electrostatic discharge protection and methods of fabrication
    4.
    发明授权
    Transistors patterned with electrostatic discharge protection and methods of fabrication 有权

    公开(公告)号：US10741542B2

    公开(公告)日：2020-08-11

    申请号：US16055365

    申请日：2018-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chien-Hsin Lee ,  Xiangxiang Lu ,  Manjunatha Prabhu ,  Mahadeva Iyer Natarajan

    IPC: H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

    Abstract: High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

    ESD device for a semiconductor structure
    7.
    发明授权
    ESD device for a semiconductor structure 有权

    公开(公告)号：US09679888B1

    公开(公告)日：2017-06-13

    申请号：US15251632

    申请日：2016-08-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chien-Hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

    IPC: H01L27/02 ,  H01L27/06 ,  H01L23/528

    CPC classification number: H01L27/0266 ,  H01L23/5286 ,  H01L27/0262 ,  H01L27/0288 ,  H01L27/0292 ,  H01L27/0623

    Abstract: An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.

    Dissipation of static charge from wiring layers during manufacturing
    10.
    发明授权
    Dissipation of static charge from wiring layers during manufacturing 有权

    公开(公告)号：US10211168B1

    公开(公告)日：2019-02-19

    申请号：US15841372

    申请日：2017-12-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Krishna M. Chavali ,  Chien-Hsin Lee ,  Mahadeva Iyer Natarajan

    IPC: H01L23/52 ,  H01L23/60 ,  H01L23/522 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528

    Abstract: Methods form integrated circuit structures that include a device layer having electronic devices on a substrate, and a multi-layer interconnect structure connected to the device layer. The multi-layer interconnect structure includes alternating insulator layers and wiring layers, power and ground wiring in the wiring layers, non-functional wiring in the wiring layers called dummy fill, and conductive vias extending through the insulator layers. The conductive vias connect the power and ground wiring in the wiring layers to the electronic devices in the device layer. The non-functional wiring is insulated from the power wiring in the wiring layer, and from the electronic devices in the device layer. The conductive vias connect the non-functional wiring (the dummy fill) in the wiring layers through the substrate, or a ground bus, thereby continuously removing static charge that would otherwise accumulate during manufacturing processes.

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