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    Silicidation of semiconductor devices
    1.
    发明授权
    Silicidation of semiconductor devices 有权
    半导体器件的硅化

    公开(公告)号：US08846467B1

    公开(公告)日：2014-09-30

    申请号：US14021525

    申请日：2013-09-09

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Roman Boschke ,  Stefan Flachowsky ,  Matthias Kessler

    IPC: H01L21/8238

    CPC classification number: H01L21/823835 ,  H01L21/823443

    Abstract: A method for performing silicidation of a gate electrode is provided that includes forming both a first transistor with a first gate electrode covered by a cap layer and a semiconductor device on the same semiconductor substrate, forming an organic planarization layer (OPL) on the first transistor and the semiconductor device, back etching the OPL such that an upper surface of the OPL is positioned at a level that is below a level of an upper surface of the cap layer, forming a mask layer covering the semiconductor device without covering the first transistor, removing the cap layer while the back-etched OPL and the mask layer are present, and performing silicidation of the first gate electrode.

    Abstract translation: 提供了一种执行栅极电极的硅化的方法，其包括在同一半导体衬底上形成第一晶体管与由盖层覆盖的第一栅电极和半导体器件，在第一晶体管上形成有机平坦化层（OPL） 和半导体器件，背面蚀刻OPL使得OPL的上表面位于低于帽层的上表面的水平的水平，形成覆盖半导体器件而不覆盖第一晶体管的掩模层， 在存在反蚀刻的OPL和掩模层的同时移除盖层，并且执行第一栅电极的硅化。

    TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS
    3.
    发明申请
    TRANSISTOR DEVICES WITH HIGH-K INSULATION LAYERS 有权
    具有高K绝缘层的晶体管器件

    公开(公告)号：US20150340362A1

    公开(公告)日：2015-11-26

    申请号：US14819646

    申请日：2015-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

    IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L27/088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

    Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

    Abstract translation: 集成电路产品包括位于第一和第二有源区域中和之上的第一和第二晶体管。 第一晶体管具有第一栅极长度和第一栅极材料堆叠，其包括具有第一厚度的第一栅极电介质层和位于第一栅极介电层上方的至少一层金属，第一栅极介电层包括一层 第一高k绝缘材料和位于第一高k绝缘材料层上的第二高k绝缘材料层。 第二晶体管具有第二栅极长度和第二栅极材料堆叠，其包括具有位于第二有源区上方的第二厚度的第二栅极介电层和位于第二栅极介电层上方的至少一层金属，第二栅极电介质 层包括第二高k绝缘材料层。

    Transistor devices with high-k insulation layers
    5.
    发明授权
    Transistor devices with high-k insulation layers 有权
    具有高k绝缘层的晶体管器件

    公开(公告)号：US09425194B2

    公开(公告)日：2016-08-23

    申请号：US14819646

    申请日：2015-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/088 ,  H01L21/28202 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7833

    Abstract: An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

    Abstract translation: 集成电路产品包括位于第一和第二有源区域中和之上的第一和第二晶体管。 第一晶体管具有第一栅极长度和第一栅极材料堆叠，其包括具有第一厚度的第一栅极电介质层和位于第一栅极介电层上方的至少一层金属，第一栅极介电层包括一层 第一高k绝缘材料和位于第一高k绝缘材料层上的第二高k绝缘材料层。 第二晶体管具有第二栅极长度和第二栅极材料堆叠，其包括具有位于第二有源区上方的第二厚度的第二栅极介电层和位于第二栅极介电层上方的至少一层金属，第二栅极电介质 层包括第二高k绝缘材料层。

    Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages
    7.
    发明授权
    Technique for manufacturing semiconductor devices comprising transistors with different threshold voltages 有权
    用于制造包括具有不同阈值电压的晶体管的半导体器件的技术

    公开(公告)号：US09219013B2

    公开(公告)日：2015-12-22

    申请号：US13799239

    申请日：2013-03-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

    IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8234

    CPC classification number: H01L21/8238 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6659

    Abstract: When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated. Furthermore, the number of implantation steps is decreased compared to conventional manufacturing processes.

    Abstract translation: 当形成包括具有不同阈值电压的晶体管的半导体器件时，相同导电类型的晶体管的不同阈值电压基本上通过执行不同的光晕注入来定义。 由于通常在同一制造步骤中进行的其它植入，例如预非晶化，源极和漏极延伸注入和额外的扩散工程注入，对于不同的阈值电压可以是相同的，除了常见的晕基植入之外，这些植入可以 在同一种植入序列中对相同导电类型的所有晶体管执行。 随后可以通过额外的低剂量晕圈注入实现特定晶体管的较高阈值电压，而另一晶体管被抗蚀剂掩模覆盖。 因此，所需抗蚀剂掩模中的注入物种的原子量减少，从而便于除去抗蚀剂掩模。 此外，与常规制造工艺相比，植入步骤的数量减少。

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