公开(公告)号：US09000564B2

公开(公告)日：2015-04-07

申请号：US13725837

申请日：2012-12-21

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc. ,  Samsung Electronics Co., Ltd.

Inventor： Pietro Montanini ,  Gerald Leake, Jr. ,  Brett H. Engel ,  Roderick Mason Miller ,  Ju Youn Kim

IPC: H01L29/00 ,  H01L49/02 ,  H01L27/06 ,  H01L27/08

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/66545

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract translation: 使用替代金属栅极（RMG）工艺提供了在金属栅极晶体管旁边创建精密多晶硅电阻的机会。 在牺牲多晶硅栅极的形成期间，也可以由相同的多晶硅膜形成精密多晶硅电阻器。 多晶硅电阻器可以稍微凹进，使得在随后用金属栅极替换牺牲栅极时，保护绝缘层可以覆盖电阻器。 使用这种工艺制造的精密多晶硅电阻器的最终结构比为具有金属栅极晶体管的集成电路提供金属电阻器的现有结构更紧凑和更不复杂。 此外，通过用掺杂剂注入多晶硅膜，调节多晶硅膜厚度或两者，可以将精密多晶硅电阻器自由地调谐为具有所需的薄层电阻。

公开(公告)号：US20140353741A1

公开(公告)日：2014-12-04

申请号：US13907690

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Pietro Montanini ,  Raymond Joy ,  Marta Mottura ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/28123 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Abstract translation: 一种制造通道长度低于50nm的增强型迁移率pFET器件的方法。 用于pFET的栅极可以在包括浅沟槽隔离（STI）结构的半导体衬底上以致密阵列图案化。 可以在用于栅极的源极和漏极区域处形成半导体衬底中的部分封闭的空隙，并且随后填充压缩地压缩栅极下方的沟道区域的外延生长的半导体。 一些栅极（伪栅极）可以在STI结构的边缘上延伸，以防止在源极和漏极区域中的外延材料的不期望的刻痕。

公开(公告)号：US09806078B1

公开(公告)日：2017-10-31

申请号：US15341240

申请日：2016-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher Prindle ,  Tenko Yamashita ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Soon-Cheon Seo

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L21/31055 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.

公开(公告)号：US10109533B1

公开(公告)日：2018-10-23

申请号：US15636725

申请日：2017-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Cheng Chi ,  Pietro Montanini ,  Tenko Yamashita ,  Nicolas Jean Loubet

IPC: H01L29/76 ,  H01L21/8238 ,  H01L27/092

Abstract: This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.

公开(公告)号：US20180254331A1

公开(公告)日：2018-09-06

申请号：US15447210

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Zhenxing Bi ,  Pietro Montanini ,  Eric R. Miller ,  Balasubramanian Pranatharthiharan ,  Oleg Gluschenkov ,  Ruqiang Bao ,  Kangguo Cheng

IPC: H01L29/66 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/3105 ,  H01L21/31053 ,  H01L29/6656

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.

公开(公告)号：US09984936B1

公开(公告)日：2018-05-29

申请号：US15651621

申请日：2017-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Siva P. Adusumilli ,  Kangguo Cheng ,  Pietro Montanini ,  Robinhsinku Chao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785

Abstract: A method includes forming a sacrificial gate and a stack of materials above a semiconductor substrate, forming a trench in each of the source/drain areas of the device, wherein each trench extends into the semiconductor substrate, forming an empty space under the sacrificial gate structure, the empty space being vertically positioned between the stack of materials and the semiconductor substrate, wherein the empty space is in communication with the trenches, performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least the sacrificial gate while at least partially filling the empty space and substantially filling the trenches, and performing a recess etching process to remove at least portions of the conformal layer positioned adjacent the sacrificial gate, thereby defining a recessed upper surface of the device isolation material.

公开(公告)号：US09685384B1

公开(公告)日：2017-06-20

申请号：US15210012

申请日：2016-07-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher Prindle ,  Soon-Cheon Seo ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Shogo Mochizuki

IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/66795

Abstract: Devices and methods of fabricating integrated circuit devices for forming epi for aggressive gate pitch are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a fin structure, a plurality of stacks; etching the spacer between the plurality of stacks; growing, epitaxially, undoped silicon on a top surface of the fin structure between the plurality of stacks; depositing a liner over the undoped silicon and the plurality of stacks; etching to remove the liner and narrow the spacers, wherein the etching forms a wider portion of the spacer at the base of the stacks; etching between the plurality of stacks to remove the undoped silicon and form recesses in the fin structure; and growing, epitaxially, doped silicon between the plurality of stacks and in the fin structure. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20190019733A1

公开(公告)日：2019-01-17

申请号：US16133850

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Cheng Chi ,  Pietro Montanini ,  Tenko Yamashita ,  Nicolas Loubet

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092

Abstract: This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.

公开(公告)号：US10109722B2

公开(公告)日：2018-10-23

申请号：US15447210

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Zhenxing Bi ,  Pietro Montanini ,  Eric R. Miller ,  Balasubramanian Pranatharthiharan ,  Oleg Gluschenkov ,  Ruqiang Bao ,  Kangguo Cheng

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/3105

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.

公开(公告)号：US20140175609A1

公开(公告)日：2014-06-26

申请号：US13725837

申请日：2012-12-21

Applicant: STMicroelectronics, Inc. ,  Samsung Electronics Co., Ltd. ,  GlobalFoundries Inc. ,  International Business Machines Corporation

Inventor： Pietro Montanini ,  Gerald Leake, JR. ,  Brett H. Engel ,  Roderick Mason Miller ,  Ju Youn Kim

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/66545

Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.

Abstract translation: 使用替代金属栅极（RMG）工艺提供了在金属栅极晶体管旁边创建精密多晶硅电阻的机会。 在牺牲多晶硅栅极的形成期间，也可以由相同的多晶硅膜形成精密多晶硅电阻器。 多晶硅电阻器可以稍微凹进，使得在随后用金属栅极替换牺牲栅极时，保护绝缘层可以覆盖电阻器。 使用这种工艺制造的精密多晶硅电阻器的最终结构比为具有金属栅极晶体管的集成电路提供金属电阻器的现有结构更紧凑和更不复杂。 此外，通过用掺杂剂注入多晶硅膜，调节多晶硅膜厚度或两者，可以将精密多晶硅电阻器自由地调谐为具有所需的薄层电阻。