公开(公告)号：US20180096839A1

公开(公告)日：2018-04-05

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han KIM ,  Wenhui WANG ,  Azat LATYPOV ,  Tamer COSKUN ,  Lei SUN

IPC: H01L21/027 ,  H01L21/66 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L21/0276 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431 ,  H01L21/823481 ,  H01L22/12 ,  H01L22/30

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

公开(公告)号：US20160365288A1

公开(公告)日：2016-12-15

申请号：US14737551

申请日：2015-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L21/8238 ,  H01L23/528 ,  H01L21/02 ,  H01L27/092 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

Abstract translation: 公开了使用虚拟栅极作为互连的工艺及其制造方法。 实施例包括在半导体衬底上形成在单元边界处的虚拟栅极结构，每个虚拟栅极结构包括一组侧壁间隔件和设置在侧壁间隔件之间的盖; 在第一伪栅极结构的第一侧上去除第一侧壁间隔物或第一盖的至少一部分，并在第一伪栅极结构上形成第一栅极接触沟槽; 以及用金属填充所述第一栅极接触沟槽以形成第一栅极接触。

公开(公告)号：US20180190588A1

公开(公告)日：2018-07-05

申请号：US15399200

申请日：2017-01-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xuelian ZHU ,  Jia ZENG ,  Wenhui WANG ,  Youngtag WOO ,  Jongwook KYE

IPC: H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0642 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.

公开(公告)号：US20150168824A1

公开(公告)日：2015-06-18

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei SUN ,  Chanro PARK ,  Wenhui WANG ,  Hui ZANG

IPC: G03F1/62 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。

公开(公告)号：US20150097263A1

公开(公告)日：2015-04-09

申请号：US14045340

申请日：2013-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan KIM ,  Jason R. CANTONE ,  Wenhui WANG

IPC: H01L21/74 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L23/528 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.

Abstract translation: 公开了一种用于通过多重图案化工艺形成接触面积的方法，其提供增加的产量并且在紧密的尖端到尖端间距的点处产生接触 - 接触短的风险以及所得到的装置。 实施例包括在晶片的平坦化表面上形成一个或多个沟槽图案化层，在一个或多个沟槽图案化层中形成一个或多个沟槽，在沿一个或多个沟槽的一个或多个点处形成阻挡掩模， 或更多的沟槽直到晶片的衬底水平，以及从一个或多个点移除阻挡掩模。

公开(公告)号：US20170141110A1

公开(公告)日：2017-05-18

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui WANG ,  Ryan Ryoung-han KIM ,  Linus JANG ,  Jason CANTONE ,  Lei SUN ,  Seowoo NAM

IPC: H01L27/092 ,  H01L27/02 ,  H01L29/06 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L23/528 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/3212 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.