公开(公告)号：US10355104B2

公开(公告)日：2019-07-16

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, Jr. ,  Shesh Mani Pandey

IPC: H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US10297675B1

公开(公告)日：2019-05-21

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US20190148492A1

公开(公告)日：2019-05-16

申请号：US15811990

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02576 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US20190131433A1

公开(公告)日：2019-05-02

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US10461155B2

公开(公告)日：2019-10-29

申请号：US15811990

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yoong Hooi Yong ,  Yanping Shen ,  Hsien-Ching Lo ,  Xusheng Wu ,  Joo Tat Ong ,  Wei Hong ,  Yi Qi ,  Dongil Choi ,  Yongjun Shi ,  Alina Vinslava ,  James Psillas ,  Hui Zang

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

公开(公告)号：US20190181243A1

公开(公告)日：2019-06-13

申请号：US16276045

申请日：2019-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/161

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US20190131432A1

公开(公告)日：2019-05-02

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, JR. ,  Shesh Mani Pandey

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.