公开(公告)号：US20170092764A1

公开(公告)日：2017-03-30

申请号：US14867193

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Andre LABONTE ,  Andreas KNORR

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7845 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

公开(公告)号：US20200098913A1

公开(公告)日：2020-03-26

申请号：US16139917

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Chanro PARK ,  Andre LABONTE ,  Daniel CHANEMOUGAME

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49

Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

公开(公告)号：US20180012798A1

公开(公告)日：2018-01-11

申请号：US15689413

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L23/535 ,  H01L23/522 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US20180012887A1

公开(公告)日：2018-01-11

申请号：US15202764

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre LABONTE ,  Ruilong XIE ,  Xunyuan ZHANG

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/78 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.