公开(公告)号：US20160300754A1

公开(公告)日：2016-10-13

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针迹。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US09275896B2

公开(公告)日：2016-03-01

申请号：US14341985

申请日：2014-07-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Deniz Elizabeth Civay ,  Ji Xu ,  Gerard Schmid ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/76802 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76897

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer.

Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使用覆盖在半导体衬底上的蚀刻层的侧壁来形成引导限制阱的图形外延生成DSA。 使用嵌段共聚物填充指向封闭的石墨电极DSA。 嵌段共聚物被相分离成可蚀刻相和耐蚀刻相。 蚀刻相位被蚀刻，同时使耐腐蚀相位基本上到位以限定具有纳米图案的蚀刻掩模。 将纳米图案转移到蚀刻层。

公开(公告)号：US10262941B2

公开(公告)日：2019-04-16

申请号：US15136384

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens ,  Tuhin Guha Neogi ,  Kai Sun ,  Deniz Elizabeth Civay ,  David Charles Pritchard ,  Andy Wei

IPC: H01L21/33 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09530689B2

公开(公告)日：2016-12-27

申请号：US14684949

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Deniz Elizabeth Civay ,  Jason Eugene Stephens ,  Jiong Li ,  Guillaume Bouche ,  Richard A. Farrell

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76811 ,  H01L21/76816

Abstract: Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.

Abstract translation: 提供了制造集成电路的方法。 一种方法包括分解用于半导体器件层的主图案布局，该半导体器件层包括目标金属线，目标金属线与目标互连通孔/触点成为第一子图案和第二子图案。 目标金属线被分解为作为第一子图案的一部分的第一线特征图案和作为第二子图案的一部分的第二线特征图案，使得第一和第二线特征图案具有限定 对应于目标互连通孔/触点的针脚。 生成对应于第一子图案的第一光掩模。 生成对应于第二子图案的第二光掩模。

公开(公告)号：US20150214113A1

公开(公告)日：2015-07-30

申请号：US14164582

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

IPC: H01L21/8234 ,  H01L29/16 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

公开(公告)号：US09576097B1

公开(公告)日：2017-02-21

申请号：US14930949

申请日：2015-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elise Laffosse ,  Deniz Elizabeth Civay

IPC: H01L21/311 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/76807 ,  Y02P90/265

Abstract: Methods and computer program products for decomposing and etching a circuit pattern layout are provided. The methods may include decomposing a circuit pattern layout into a first sub-pattern and second sub-pattern, where the decomposing includes: identifying, from the circuit pattern layout, a design line and a design via location associated with the design line; forming a first pattern line for the first sub-pattern corresponding to a first portion of the design line, and a second pattern line for the second sub-pattern corresponding to a second portion of the design line, with the first and second pattern lines overlapping at the design via location in an overlay of the first sub-pattern with the second sub-pattern. The first sub-pattern may be etched in a first circuit structure layer and the second sub-pattern etched in a second circuit structure layer, the etching at least partially forming a via at the design via location.

Abstract translation: 提供了用于分解和蚀刻电路图案布局的方法和计算机程序产品。 所述方法可以包括将电路图案布局分解为第一子图案和第二子图案，其中分解包括：通过与设计线相关联的位置从电路图案布局识别设计线和设计; 形成对应于设计线的第一部分的第一子图案的第一图案线和对应于设计线的第二部分的第二子图案的第二图案线，其中第一和第二图案线重叠 在通过第一子图案与第二子图案的重叠的位置处的设计。 可以在第一电路结构层中蚀刻第一子图案，并且在第二电路结构层中蚀刻第二子图案，蚀刻至少部分地在设计经过位置形成通孔。

公开(公告)号：US09397004B2

公开(公告)日：2016-07-19

申请号：US14164582

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。