公开(公告)号：US20170200792A1

公开(公告)日：2017-07-13

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho MAENG ,  Andy WEI ,  Anthony OZZELLO ,  Bharat KRISHNAN ,  Guillaume BOUCHE ,  Haifeng SHENG ,  Haigou HUANG ,  Huang LIU ,  Huy M. CAO ,  Ja-Hyung HAN ,  SangWoo LIM ,  Kenneth A. BATES ,  Shyam PAL ,  Xintuo DAI ,  Jinping LIU

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20180350607A1

公开(公告)日：2018-12-06

申请号：US15611231

申请日：2017-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui SHU ,  Haifeng SHENG ,  Jinping LIU

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to methods to remove a contact etch stop layer without consuming material of a self-aligned contact (SAC) layer. The method includes: forming a gate structure on a substrate; forming a capping layer on the gate structure; forming a contact etch stop layer of a first material, adjacent to the gate metal structure; converting the contact etch stop layer to a second material which is different than the capping layer; and selectively removing the second material without completely removing the capping layer.

公开(公告)号：US20180012760A1

公开(公告)日：2018-01-11

申请号：US15674763

申请日：2017-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui SHU ,  Daniel JAEGER ,  Garo Jacques DERDERIAN ,  Haifeng SHENG ,  Jinping LIU

IPC: H01L21/033 ,  H01L27/11

CPC classification number: H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.