公开(公告)号：US20150035062A1

公开(公告)日：2015-02-05

申请号：US13954289

申请日：2013-07-30

申请人： GLOBALFOUNDRIES, INC.

发明人： Jinping LIU ,  Bharat KRISHNAN ,  Bongki LEE ,  Vidmantas SARGUNAS ,  Weihua TONG ,  Seung KIM

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface. A gate is formed overlying the first side and second side of the channel region. The method includes implanting ions into the channel region through the exposed first end surface and the exposed second end surface. Further, the method includes forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括：具有第一侧，第二侧，暴露的第一端面和暴露的第二端面的翅片结构的沟道区。 形成在沟道区域的第一侧和第二侧上方的栅极。 该方法包括通过暴露的第一端表面和暴露的第二端表面将离子注入沟道区域。 此外，所述方法包括在所述通道区域的暴露的第一端面和暴露的第二端面附近形成所述鳍结构的源极/漏极区域。

公开(公告)号：US20170256624A1

公开(公告)日：2017-09-07

申请号：US15060761

申请日：2016-03-04

申请人： GLOBALFOUNDRIES Inc.

发明人： Tek Po Rinus LEE ,  Jinping LIU ,  Ruilong XIE

IPC分类号： H01L29/47 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/40 ,  H01L27/092

CPC分类号： H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

摘要： Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include providing a substrate having an n-FET region and a p-FET region, each region including a gate between source/drain regions; applying a mask over the n-FET region; selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked; removing the mask; depositing a titanium-based metal over the n-FET and p-FET region source/drain regions; and microwave annealing.

公开(公告)号：US20170200792A1

公开(公告)日：2017-07-13

申请号：US14993537

申请日：2016-01-12

申请人： GLOBALFOUNDRIES Inc.

发明人： Chang Ho MAENG ,  Andy WEI ,  Anthony OZZELLO ,  Bharat KRISHNAN ,  Guillaume BOUCHE ,  Haifeng SHENG ,  Haigou HUANG ,  Huang LIU ,  Huy M. CAO ,  Ja-Hyung HAN ,  SangWoo LIM ,  Kenneth A. BATES ,  Shyam PAL ,  Xintuo DAI ,  Jinping LIU

IPC分类号： H01L29/40 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423

CPC分类号： H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

摘要： Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.

公开(公告)号：US20190305105A1

公开(公告)日：2019-10-03

申请号：US15943272

申请日：2018-04-02

申请人： GLOBALFOUNDRIES Inc.

发明人： Qun GAO ,  Christopher NASSAR ,  Sugirtha KRISHNAMURTHY ,  Domingo Antonio FERRER LUPPI ,  John SPORRE ,  Shahab SIDDIQUI ,  Beth BAUMERT ,  Abu ZAINUDDIN ,  Jinping LIU ,  Tae Jeong LEE ,  Luigi PANTISANO ,  Heather LAZAR ,  Hui ZANG

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423

摘要： A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.

公开(公告)号：US20190228976A1

公开(公告)日：2019-07-25

申请号：US15876407

申请日：2018-01-22

申请人： GLOBALFOUNDRIES INC.

发明人： Haigou HUANG ,  Jinsheng GAO ,  Hong YU ,  Jinping LIU ,  Huang LIU

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

摘要： The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.

公开(公告)号：US20180350607A1

公开(公告)日：2018-12-06

申请号：US15611231

申请日：2017-06-01

申请人： GLOBALFOUNDRIES INC.

发明人： Jiehui SHU ,  Haifeng SHENG ,  Jinping LIU

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

摘要： The present disclosure relates to semiconductor structures and, more particularly, to methods to remove a contact etch stop layer without consuming material of a self-aligned contact (SAC) layer. The method includes: forming a gate structure on a substrate; forming a capping layer on the gate structure; forming a contact etch stop layer of a first material, adjacent to the gate metal structure; converting the contact etch stop layer to a second material which is different than the capping layer; and selectively removing the second material without completely removing the capping layer.

公开(公告)号：US20180330994A1

公开(公告)日：2018-11-15

申请号：US15590195

申请日：2017-05-09

申请人： GLOBALFOUNDRIES INC.

发明人： Hui ZANG ,  Jinping LIU

IPC分类号： H01L21/8234 ,  H01L29/417

CPC分类号： H01L21/823431 ,  H01L21/0217 ,  H01L21/02348 ,  H01L27/0886 ,  H01L29/41791

摘要： A multi-masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch and fin critical dimension within different arrays. A layer of curable silicon nitride is incorporated into a patterning architecture, patterned to form an etch mask, and locally cured to further modify the etch mask geometry. The use of cured and uncured structures facilitate the tuning of the resultant fin geometry.

公开(公告)号：US20180138177A1

公开(公告)日：2018-05-17

申请号：US15352963

申请日：2016-11-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Tek Po Rinus LEE ,  Bharat KRISHNAN ,  Jinping LIU ,  Hui ZANG ,  Judson Robert HOLT

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/3205 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456

摘要： Formation of band-edge contacts include, for example, providing an intermediate semiconductor structure comprising a substrate and a gate thereon and source/drain regions adjacent the gate, depositing a non-epitaxial layer on the source/drain regions, deposing a metal layer on the non-epitaxial layer, and forming metal alloy contacts from the deposited non-epitaxial layer and metal layer on the source/drain regions by annealing the deposited non-epitaxial layer and metal layer.

公开(公告)号：US20180012760A1

公开(公告)日：2018-01-11

申请号：US15674763

申请日：2017-08-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Jiehui SHU ,  Daniel JAEGER ,  Garo Jacques DERDERIAN ,  Haifeng SHENG ,  Jinping LIU

IPC分类号： H01L21/033 ,  H01L27/11

CPC分类号： H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

摘要： Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

公开(公告)号：US20180006155A1

公开(公告)日：2018-01-04

申请号：US15197892

申请日：2016-06-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Robert Judson HOLT ,  Jinping LIU ,  Jody FRONHEISER ,  Bharat KRISHNAN ,  Churamani GAIRE ,  Timothy James MCARDLE ,  Murat Kerem AKARVARDAR

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L27/088 ,  H01L21/762

CPC分类号： H01L21/02694 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/76224 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

摘要： A method of forming defect-free relaxed SiGe fins is provided. Embodiments include forming fully strained defect-free SiGe fins on a first portion of a Si substrate; forming Si fins on a second portion of the Si substrate; forming STI regions between adjacent SiGe fins and Si fins; forming a cladding layer over top and side surfaces of the SiGe fins and the Si fins and over the STI regions in the second portion of the Si substrate; recessing the STI regions on the first portion of the Si substrate, revealing a bottom portion of the SiGe fins; implanting dopant into the Si substrate below the SiGe fins; and annealing.