公开(公告)号：US20160204098A1

公开(公告)日：2016-07-14

申请号：US15080090

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L27/02 ,  H01L21/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

公开(公告)号：US10529704B1

公开(公告)日：2020-01-07

申请号：US16148323

申请日：2018-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Salvatore Cimino ,  David Pritchard ,  Lixia Lei ,  Heng Yang ,  Manjunatha Prabhu

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/06

Abstract: One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.

公开(公告)号：US20160005828A1

公开(公告)日：2016-01-07

申请号：US14321679

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L29/423 ,  H01L29/08 ,  H01L21/28 ,  G01R31/26 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/66 ,  H01L21/762

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Abstract translation: 本文公开的至少一种方法，装置和系统包括形成包括晶体管的器件，晶体管包括与有源栅极并联的至少一个非活性栅极。 形成基板上的源极区域。 在邻近源极区域的衬底上形成有源栅极区域。 在邻近有源栅极区的衬底上形成漏极区。 第一非活性栅极区域平行于有源栅极区域形成在衬底上。 源极区域，漏极区域，有源栅极区域和第一非活性栅极区域包括晶体管。 第一非活性栅极区域能够耗散电荷的至少一部分。

公开(公告)号：US20210057558A1

公开(公告)日：2021-02-25

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US09324822B2

公开(公告)日：2016-04-26

申请号：US14321679

申请日：2014-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andreas Kerber ,  Suresh Uppal ,  Salvatore Cimino ,  Hao Jiang

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/423 ,  H01L21/66 ,  H01L29/08 ,  H01L21/28 ,  H01L21/762 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  G01R31/26

CPC classification number: H01L27/0296 ,  G01R31/2621 ,  H01L21/28035 ,  H01L21/76224 ,  H01L22/30 ,  H01L22/34 ,  H01L27/0288 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42364 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/78

Abstract: At least one method, apparatus and system disclosed herein involves forming a device comprising a transistor comprising an active gate and at least one inactive gate in parallel to the active gate. A source region on a substrate is formed. An active gate region is formed on the substrate adjacent the source region. A drain region is formed on the substrate adjacent the active gate region. A first inactive gate region is formed on the substrate in parallel to the active gate region. The source region, the drain region, the active gate region, and the first inactive gate region comprise the transistor. The first inactive gate region is capable of dissipating the at least a portion of a charge.

Abstract translation: 本文公开的至少一种方法，装置和系统包括形成包括晶体管的器件，晶体管包括与有源栅极并联的至少一个非活性栅极。 形成基板上的源极区域。 在邻近源极区域的衬底上形成有源栅极区域。 在邻近有源栅极区的衬底上形成漏极区。 第一非活性栅极区域平行于有源栅极区域形成在衬底上。 源极区域，漏极区域，有源栅极区域和第一非活性栅极区域包括晶体管。 第一非活性栅极区域能够耗散电荷的至少一部分。