公开(公告)号：US20240128328A1

公开(公告)日：2024-04-18

申请号：US17964356

申请日：2022-10-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michael J. ZIERAK ,  Steven J. BENTLEY ,  Santosh SHARMA ,  Mark D. LEVY ,  Johnatan A. KANTAROVSKY

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/402 ,  H01L29/2003 ,  H01L29/6656 ,  H01L29/7786

Abstract: The present disclosure relates to a structure which includes at least one gate structure over semiconductor material, the at least one gate structure comprising an active layer, a gate metal extending from the active layer and a sidewall spacer on sidewalls of the gate metal, and a field plate aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.

公开(公告)号：US20230117591A1

公开(公告)日：2023-04-20

申请号：US17504051

申请日：2021-10-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Richard J. RASSEL ,  Johnatan A. KANTAROVSKY ,  Zhong-Xiang HE ,  Mark D. LEVY ,  Michel J. ABOU-KHALIL

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.

公开(公告)号：US20220262900A1

公开(公告)日：2022-08-18

申请号：US17738179

申请日：2022-05-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma RANA ,  Anthony K. STAMPER ,  Johnatan A. KANTAROVSKY ,  Steven M. SHANK ,  Siva P. ADUSUMILLI

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/763 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US20220173211A1

公开(公告)日：2022-06-02

申请号：US17108543

申请日：2020-12-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Brett T. CUCCI ,  Siva P. ADUSUMILLI ,  Johnatan A. KANTAROVSKY ,  Claire E. KARDOS ,  Sen LIU

IPC: H01L29/06 ,  H01L21/764 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.

公开(公告)号：US20250040221A1

公开(公告)日：2025-01-30

申请号：US18226982

申请日：2023-07-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. KANTAROVSKY ,  Mark D. LEVY ,  Alvin J. JOSEPH ,  Santosh SHARMA ,  Michael J. ZIERAK

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.

公开(公告)号：US20240178310A1

公开(公告)日：2024-05-30

申请号：US18070800

申请日：2022-11-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh SHARMA ,  Rajendran KRISHNASAMY ,  Johnatan A. KANTAROVSKY

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; and a channel region under the gate structure, the channel region having a first portion including a first thickness and a second portion having a second thickness greater than the first thickness, the second portion being positioned remotely from the gate structure.

公开(公告)号：US20240088242A1

公开(公告)日：2024-03-14

申请号：US17943925

申请日：2022-09-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. KANTAROVSKY ,  Rebouh BENELBAR ,  Ajay RAMAN ,  Michel J. ABOU-KHALIL ,  Rajendran KRISHNASAMY ,  Randy L. WOLF

IPC: H01L29/417 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors and methods of manufacture. A structure includes: a semiconductor layer on a semiconductor material; a gate structure on the semiconductor layer; a drain region comprising the semiconductor layer and which is adjacent to the gate structure; an ohmic contact which includes at least one terminal connection connecting to the semiconductor material, the ohmic contact being adjacent to the drain region and spaced away from the gate structure; and a capacitance reducing structure adjacent to the drain region.

公开(公告)号：US20240145469A1

公开(公告)日：2024-05-02

申请号：US17974005

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh SHARMA ,  Johnatan A. KANTAROVSKY

IPC: H01L27/088 ,  H01L27/10 ,  H01L29/20

CPC classification number: H01L27/0883 ,  H01L27/101 ,  H01L29/2003

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a depletion mode device with a programmable element used for chip programming and circuit configuration and methods of manufacture and operation. In particular, the structure includes a programmable element on an active layer of semiconductor material, and a depletion mode device comprising a dual gate connected to the programmable element.

公开(公告)号：US20220238646A1

公开(公告)日：2022-07-28

申请号：US17157269

申请日：2021-01-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. LEVY ,  Siva P. ADUSUMILLI ,  Johnatan A. KANTAROVSKY ,  Vibhor JAIN

IPC: H01L29/06 ,  H01L29/08 ,  H01L27/07 ,  H01L27/06 ,  H01L21/308 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

公开(公告)号：US20220115329A1

公开(公告)日：2022-04-14

申请号：US17070377

申请日：2020-10-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. KANTAROVSKY ,  Vibhor JAIN ,  Siva P. ADUSUMILLI ,  Ajay RAMAN ,  Sebastian T. VENTRONE ,  Yves T. NGU

IPC: H01L23/552 ,  H01L23/00 ,  H01L49/02 ,  H01L23/522

Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.