公开(公告)号：US12166476B2

公开(公告)日：2024-12-10

申请号：US18065768

申请日：2022-12-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy

IPC: H03K17/08 ,  H01L29/40 ,  H01L29/78

Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

公开(公告)号：US12154956B1

公开(公告)日：2024-11-26

申请号：US18632902

申请日：2024-04-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Mark D. Levy ,  John J. Ellis-Monaghan ,  Michael J. Zierak ,  Kristin Marie Welch

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.

公开(公告)号：US20250089284A1

公开(公告)日：2025-03-13

申请号：US18243910

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Michael J. Zierak ,  Santosh Sharma ,  Mark D. Levy ,  Steven J. Bentley

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778

Abstract: A structure according to the disclosure includes a dielectric layer over a substrate and horizontally between a gate terminal and a source/drain (S/D) terminal. The dielectric layer has a first surface proximal to the substrate and a second surface opposite the first surface. The dielectric layer has a plurality of recesses in the second surface. At least some of the plurality of recesses have different depths. A conductive field plate includes a metal layer on the second surface and within the plurality of recesses. The conductive field plate is electrically isolated from the gate terminal and the S/D terminal.

公开(公告)号：US20240085247A1

公开(公告)日：2024-03-14

申请号：US17931670

申请日：2022-09-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Johnatan Avraham Kantarovsky

IPC: G01K7/18 ,  H01C7/04 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: G01K7/183 ,  H01C7/041 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

公开(公告)号：US11616127B2

公开(公告)日：2023-03-28

申请号：US17650854

申请日：2022-02-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Siva P. Adusumilli ,  Steven Bentley ,  Michael Joseph Zierak ,  Jeonghyun Hwang

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/417

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

公开(公告)号：US12255235B2

公开(公告)日：2025-03-18

申请号：US17645738

申请日：2021-12-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky

IPC: H01L29/40 ,  H01L21/76 ,  H01L21/765 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

Abstract: A transistor structure is provided, the transistor structure comprising a source, a drain, and a gate between the source and the drain. The gate may have a top surface. A first field plate may be between the source and the drain. The first field plate may be L-shaped and having a vertical portion over a horizontal portion. A top surface of the vertical portion of the first field plate may be at least as high as the top surface of the gate. A second field plate, whereby the second field plate may be connected to the gate and the second field plate may partially overlap the horizontal portion of the first field plate.

公开(公告)号：US12243935B2

公开(公告)日：2025-03-04

申请号：US18487114

申请日：2023-10-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vibhor Jain ,  Johnatan Avraham Kantarovsky ,  Mark David Levy ,  Ephrem Gebreselasie ,  Yves Ngu ,  Siva P. Adusumilli

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/43 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US20240204764A1

公开(公告)日：2024-06-20

申请号：US18065768

申请日：2022-12-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy

IPC: H03K17/08 ,  H01L29/40 ,  H01L29/78

CPC classification number: H03K17/08 ,  H01L29/404 ,  H01L29/7816

Abstract: An integrated circuit (IC) having a high voltage semiconductor device with a plurality of field plates between the gate and drain. The IC further includes a biasing circuit electrically coupled to each of the plurality of field plates, the biasing circuit including a plurality of high voltage depletion mode transistors, each having a pinch off voltage. The high voltage depletion mode transistors may have different pinch off voltages, and each of the field plates are each independently biased by a different one of the high voltage depletion mode transistors.

公开(公告)号：US11923446B2

公开(公告)日：2024-03-05

申请号：US17503345

申请日：2021-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Johnatan Avraham Kantarovsky ,  Mark David Levy ,  Ephrem Gebreselasie ,  Yves Ngu ,  Siva P. Adusumilli

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L29/43

CPC classification number: H01L29/7781 ,  H01L29/407 ,  H01L29/435 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/66431

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

公开(公告)号：US11316019B2

公开(公告)日：2022-04-26

申请号：US16942734

申请日：2020-07-29

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Siva P. Adusumilli ,  Steven Bentley ,  Michael Joseph Zierak ,  Jeonghyun Hwang

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.