公开(公告)号：US11658177B2

公开(公告)日：2023-05-23

申请号：US17113473

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Michel J. Abou-Khalil ,  John J. Ellis-Monaghan ,  Randy Wolf ,  Alvin J. Joseph ,  Aaron Vallett

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0285 ,  H01L27/0218 ,  H01L29/0619 ,  H01L29/0649

Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

公开(公告)号：US11637068B2

公开(公告)日：2023-04-25

申请号：US17121810

申请日：2020-12-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L27/06

Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

公开(公告)号：US11581450B2

公开(公告)日：2023-02-14

申请号：US16899028

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L31/101 ,  H01L31/107 ,  H01L31/18 ,  H01L31/0352

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

公开(公告)号：US20220308297A1

公开(公告)日：2022-09-29

申请号：US17209416

申请日：2021-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  John J. Ellis-Monaghan ,  Frank G. Kuechenmeister ,  Jae Kyu Cho ,  Michal Rakowski

IPC: G02B6/42 ,  H01L23/00

Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.

公开(公告)号：US20220291126A1

公开(公告)日：2022-09-15

申请号：US17195887

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik ,  Yusheng Bian

IPC: G01N21/64 ,  H01L31/12 ,  H01L31/02 ,  H01L31/0232 ,  G01N21/85

Abstract: A “lab on a chip” includes an optofluidic sensor and components to analyze signals from the optofluidic sensor. The optofluidic sensor includes a substrate, a channel at least partially defined by a portion of a layer of first material on the substrate, input and output fluid reservoirs in fluid communication with the channel, at least a first radiation source coupled to the substrate adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent and below the channel.

公开(公告)号：US20220189877A1

公开(公告)日：2022-06-16

申请号：US17121810

申请日：2020-12-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373

Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

公开(公告)号：US20220181452A1

公开(公告)日：2022-06-09

申请号：US17151343

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Ellis-Monaghan ,  Anupam Dutta ,  Satyasuresh V. Choppalli ,  Venkata N.R. Vanukuru ,  Michel Abou-Khalil

IPC: H01L29/40 ,  H01L29/78

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

公开(公告)号：US20220181361A1

公开(公告)日：2022-06-09

申请号：US17113418

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy ,  Ramsey Hazbun

IPC: H01L27/144 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/18

Abstract: Structures including multiple photodiodes and methods of fabricating a structure including multiple photodiodes. A substrate has a first trench extending to a first depth into the substrate and a second trench extending to a second depth into the substrate that is greater than the first depth. A first photodiode includes a first light-absorbing layer containing a first material positioned in the first trench. A second photodiode includes a second light-absorbing layer containing a second material positioned in the second trench. The first material and the second material each include germanium.

公开(公告)号：US20220181317A1

公开(公告)日：2022-06-09

申请号：US17113473

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Michel J. Abou-Khalil ,  John J. Ellis-Monaghan ,  Randy Wolf ,  Alvin J. Joseph ,  Aaron Vallett

IPC: H01L27/02 ,  H01L29/06

Abstract: Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

公开(公告)号：US11315825B2

公开(公告)日：2022-04-26

申请号：US16553737

申请日：2019-08-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Aaron Vallett ,  Steven M. Shank ,  Bojidha Babu ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324

Abstract: Structures including electrical isolation and methods associated with forming such structures. A semiconductor layer has a top surface, a polycrystalline region, and a single-crystal region between the polycrystalline region and the top surface. An isolation band is located beneath the single-crystal region. The isolation band contains a first concentration of an n-type dopant and a second concentration of a p-type dopant, and a net difference between the first concentration and the second concentration is within a range of about five percent to about fifteen percent.