公开(公告)号：US20070083342A1

公开(公告)日：2007-04-12

申请号：US11469706

申请日：2006-09-01

申请人： Hiroshi WATANABE ,  Atsuhiro KINOSHITA

发明人： Hiroshi WATANABE ,  Atsuhiro KINOSHITA

IPC分类号： G04F10/00

CPC分类号： G04F10/10

摘要： An electronic timer having a parallel unit, a current detecting unit, and a time measuring unit. The parallel unit is formed of a plurality of aging devices connected in parallel and configured to be turned on or off for a predetermined time after storing electric charges. Each aging device is a transistor which includes a floating gate. The current detecting unit detects a sum current flowing in the parallel unit when a voltage is applied between input and output terminals of the parallel unit. The time measuring unit measures a time required to resume the supplying of power after the interruption of power supplying, from the sum current detected by the current detecting unit.

摘要翻译： 具有并联单元，电流检测单元和时间测量单元的电子计时器。 并联单元由并联连接的多个老化装置形成，并且在存储电荷之后被配置为开启或关闭预定时间。 每个老化装置是包括浮动栅极的晶体管。 当在并行单元的输入和输出端之间施加电压时，电流检测单元检测在并联单元中流动的和电流。 所述时间测量单元根据由所述电流检测单元检测到的和电流来测量在供电中断之后恢复供电所需的时间。

公开(公告)号：US20080111178A1

公开(公告)日：2008-05-15

申请号：US11835694

申请日：2007-08-08

申请人： Atsuhiro KINOSHITA ,  Hiroshi Watanabe ,  Fumitaka Arai

发明人： Atsuhiro KINOSHITA ,  Hiroshi Watanabe ,  Fumitaka Arai

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.

摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。

公开(公告)号：US20100270607A1

公开(公告)日：2010-10-28

申请号：US12831323

申请日：2010-07-07

申请人： Atsuhiro KINOSHITA ,  Hiroshi Watanabe ,  Fumitaka Arai

发明人： Atsuhiro KINOSHITA ,  Hiroshi Watanabe ,  Fumitaka Arai

IPC分类号： H01L29/788

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： It is made possible to provide a memory device that can be made very small in size and have a high capacity while being able to effectively suppress short-channel effects. A nonvolatile semiconductor memory device includes: a first insulating film formed on a semiconductor substrate; a semiconductor layer formed above the semiconductor substrate so that the first insulating film is interposed between the semiconductor layer and the semiconductor substrate; a NAND cell having a plurality of memory cell transistors connected in series, each of the memory cell transistors having a gate insulating film formed on the semiconductor layer, a floating gate formed on the gate insulating film, a second insulating film formed on the floating gate, and a control gate formed on the second insulating film; a source region having an impurity diffusion layer formed in one side of the NAND cell; and a drain region having a metal electrode formed in the other side of the NAND cell.

摘要翻译： 可以提供一种可以制造尺寸非常小并且具有高容量的存储器件，同时能够有效地抑制短沟道效应。 非易失性半导体存储器件包括：形成在半导体衬底上的第一绝缘膜; 半导体层，其形成在所述半导体衬底上方，使得所述第一绝缘膜插入在所述半导体层和所述半导体衬底之间; 具有串联连接的多个存储单元晶体管的NAND单元，每个存储单元晶体管具有形成在所述半导体层上的栅极绝缘膜，形成在所述栅极绝缘膜上的浮置栅极，形成在所述浮动栅极上的第二绝缘膜 以及形成在所述第二绝缘膜上的控制栅极; 源区，其具有形成在NAND单元的一侧的杂质扩散层; 以及在NAND单元的另一侧形成有金属电极的漏极区域。

公开(公告)号：US20130181184A1

公开(公告)日：2013-07-18

申请号：US13547567

申请日：2012-07-12

申请人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

发明人： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

IPC分类号： H01L27/24 ,  H01L21/8234

CPC分类号： H01L45/1233 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/222 ,  H01L27/2454 ,  H01L27/2481 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/1206 ,  H01L45/1253

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

公开(公告)号：US20090250742A1

公开(公告)日：2009-10-08

申请号：US12043193

申请日：2008-03-06

申请人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi

发明人： Atsuhiro KINOSHITA ,  Yoshifumi Nishi

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/785

摘要： A neuron device includes: a semiconductor layer; source and drain regions formed in the semiconductor layer at a distance from each other; a protection film formed on an upper face of the semiconductor layer; a channel region formed in the semiconductor layer between the source region and the drain region; a pair of gate insulating films formed on two side faces of the channel region; a floating gate electrode including: a first portion covered on the gate insulating films and the protection film; a second portion connected to the first portion; and a third portion provided on the substrate so as to connect to the end portion of the second portion on the opposite side from the first portion; an interelectrode insulating film provided on the first to third portions; and a plurality of control gate electrodes provided on the third portion.

摘要翻译： 神经元装置包括：半导体层; 源极和漏极区域形成在半导体层中彼此间隔一定距离; 形成在所述半导体层的上表面上的保护膜; 在所述源极区域和所述漏极区域之间的所述半导体层中形成的沟道区域; 形成在沟道区域的两个侧面上的一对栅极绝缘膜; 一种浮栅电极，包括：覆盖在栅极绝缘膜和保护膜上的第一部分; 连接到第一部分的第二部分; 以及第三部分，设置在所述基板上，以便在与所述第一部分相反的一侧连接到所述第二部分的端部; 设置在所述第一至第三部分上的电极间绝缘膜; 以及设置在第三部分上的多个控制栅电极。

公开(公告)号：US20140035618A1

公开(公告)日：2014-02-06

申请号：US13613701

申请日：2012-09-13

申请人： Kosuke TATSUMURA ,  Masato ODA ,  Atsuhiro KINOSHITA ,  Koichiro ZAITSU ,  Mari MATSUMOTO ,  Shinichi YASUDA

发明人： Kosuke TATSUMURA ,  Masato ODA ,  Atsuhiro KINOSHITA ,  Koichiro ZAITSU ,  Mari MATSUMOTO ,  Shinichi YASUDA

IPC分类号： H03K19/177

CPC分类号： H03K19/17728 ,  G11C15/04 ,  G11C15/046 ,  H03K19/17712

摘要： A circuit according to embodiments includes: a plurality of bit-string comparators each of which includes a plurality of single-bit comparators each of which includes first and second input terminals, first and second match-determination terminals, and a memory storing data and inverted data in a pair, the first input terminal being connected to a respective search line, the second input terminal being connected to an inverted search line being paired with the respective search line, and a matching line connecting the first and second match-determination terminals of the single-bit comparators; a pre-charge transistor of which source is connected to a supply voltage line; a common matching line connected to a drain of the pre-charge transistor and the matching lines of the bit-string comparators; and an output inverter of which input is connected to the common matching line.

摘要翻译： 根据实施例的电路包括：多个比特串比较器，每个比特串包括多个单比特比较器，每个单比特比较器包括第一和第二输入端，第一和第二匹配确定终端，以及存储数据并反转的存储器 成对的数据，第一输入端子连接到相应的搜索线，第二输入端子连接到与相应搜索线配对的反向搜索线，以及匹配线，连接第一和第二匹配确定端子 单比特比较器; 其源极连接到电源电压线的预充电晶体管; 连接到预充电晶体管的漏极和位串比较器的匹配线的公共匹配线; 以及输入反相器，其输入连接到公共匹配线。

公开(公告)号：US20120218802A1

公开(公告)日：2012-08-30

申请号：US13403398

申请日：2012-02-23

申请人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

发明人： Takao MARUKAME ,  Tomoaki INOKUCHI ,  Hideyuki SUGIYAMA ,  Mizue ISHIKAWA ,  Yoshiaki SAITO ,  Atsuhiro KINOSHITA ,  Kosuke TATSUMURA

IPC分类号： G11C15/02

CPC分类号： G11C15/02 ,  G11C11/161 ,  G11C15/046 ,  H01L27/228

摘要： One embodiment provides a content addressable memory, including: a pair of spin MOSFETs including: a first spin MOSFET whose magnetization state is set in accordance with stored data; and a second spin MOSFET whose magnetization state is set in accordance with the stored data, the second spin MOSFET being connected in parallel with the first spin MOSFET; a first wiring configured to apply a gate voltage so that any one of the first spin MOSFET and the second spin MOSFET becomes electrically conductive in accordance with search data; and a second wiring configured to apply a current to both of the first spin MOSFET and the second spin MOSFET.

摘要翻译： 一个实施例提供一种内容可寻址存储器，包括：一对自旋MOSFET，其包括：第一自旋MOSFET，其磁化状态根据存储的数据设置; 以及第二自旋MOSFET，其磁化状态根据存储的数据设定，第二自旋MOSFET与第一自旋MOSFET并联连接; 第一布线，被配置为施加栅极电压，使得第一自旋MOSFET和第二自旋MOSFET中的任何一个根据搜索数据变为导电; 以及配置为向第一自旋MOSFET和第二自旋MOSFET两者施加电流的第二布线。

公开(公告)号：US20120068241A1

公开(公告)日：2012-03-22

申请号：US13236734

申请日：2011-09-20

申请人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

发明人： Kiwamu SAKUMA ,  Atsuhiro KINOSHITA

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/785 ,  H01L29/792

摘要： According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure.

摘要翻译： 根据一个实施例，存储器件包括第一和第二鳍式堆叠结构，每个第一和第二鳍式堆叠结构每个包括沿第一方向堆叠的第一至第i存储器串（i是除1之外的自然数），第一和第二鳍式堆叠结构 其在第二方向上延伸并且在第三方向上相邻，第一部分连接到第一鳍式堆叠结构的第二方向上的一端，第一部分的第三方向上的宽度大于第一方向上的宽度 第一鳍式堆叠结构的第三方向和与第二鳍式堆叠结构的第二方向的一端连接的第二部分，第二部分的第三方向上的宽度大于第三方向上的宽度 的第二鳍式堆叠结构。

公开(公告)号：US20130198445A1

公开(公告)日：2013-08-01

申请号：US13557401

申请日：2012-07-25

申请人： Yosuke BANDO ,  Atsuhiro KINOSHITA ,  Atsushi KUNIMATSU

发明人： Yosuke BANDO ,  Atsuhiro KINOSHITA ,  Atsushi KUNIMATSU

IPC分类号： G11C15/04

CPC分类号： G11C15/04 ,  G06F17/30864 ,  G06F17/30949 ,  G06F17/30985 ,  G11C15/00

摘要： According to one embodiment, a semiconductor memory device includes a memory and a controller. The memory stores data pieces and search information including entries, where each entry is associated with a search key for specifying one data piece and a real address at which the data piece is stored. Upon reception of a first command, the controller, when the first command specifies a search key, outputs one data piece corresponding to one entry which includes the search key, and when the first command specifies one real address, outputs one data piece corresponding to one entry including the real address.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器和控制器。 存储器存储包括条目的数据片段和搜索信息，其中每个条目与用于指定一个数据片段的搜索关键字和存储数据片段的实际地址相关联。 当接收到第一命令时，控制器在第一命令指定搜索关键字时，输出与包括搜索关键字的一个条目相对应的一个数据段，并且当第一命令指定一个实际地址时，输出与一个对应的一个数据 输入包括真实地址。

公开(公告)号：US20130042055A1

公开(公告)日：2013-02-14

申请号：US13569542

申请日：2012-08-08

申请人： Atsuhiro KINOSHITA ,  Takao Marukame ,  Kosuke Tatsumura

发明人： Atsuhiro KINOSHITA ,  Takao Marukame ,  Kosuke Tatsumura

IPC分类号： G06F12/06 ,  G06F12/02 ,  G06F12/00

CPC分类号： G06F17/30587 ,  G06F12/0292

摘要： According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.

摘要翻译： 根据一个实施例，包括包含键值数据作为一对键和与该键对应的值的键值存储器的存储器系统包括第一存储器，控制电路和第二存储器。 第一存储器被配置为包含用于存储数据的数据区域和包含键值数据的表区域。 控制电路被配置为通过寻址来执行对第一存储器的写入和读取，并且基于键值存储执行请求。 第二存储器被配置为根据来自控制电路的指令存储键值数据。 控制电路通过使用存储在第一存储器中的键值数据和存储在第二存储器中的键值数据来执行设置操作。