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公开(公告)号：US11462520B2
公开(公告)日：2022-10-04
申请号：US15922932
申请日：2018-03-16
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Abstract: The present invention provides a chip integration module, including a die, a passive device, and a connecting piece, where the die is provided with a die bonding portion, the passive device is provided with a passive device bonding portion, the die bonding portion of the die and the passive device bonding portion of the passive device are disposed opposite to each other, and the connecting piece is disposed between the die bonding portion and the passive device bonding portion and is connected to the die bonding portion and the passive device bonding portion. The chip integration module of the present invention achieves easy integration and has low costs. Moreover, a path connecting the die to the passive device becomes shorter, which can improve performance of the passive device. The present invention further discloses a chip package structure and a chip integration method.
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公开(公告)号：US20180114760A1
公开(公告)日：2018-04-26
申请号：US15792307
申请日：2017-10-24
Applicant: Huawei Technologies Co., Ltd.
Inventor： HuiLi Fu , Jianwei Guo , Tiejun Liu
IPC: H01L23/00 , H01L23/498 , H01L21/48 , H01L23/31 , H01L23/66
CPC classification number: H01L23/562 , H01L21/4857 , H01L23/3185 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L23/66 , H01L24/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16152 , H01L2924/00
Abstract: A package substrate, including a first reference layer and a second reference layer disposed opposite to each other, a first composite layer disposed on a side of the first reference layer and close to the second reference layer, a second composite layer disposed on a side of the second reference layer and close to the first reference layer, and a metal trace is laminated between the first composite layer and the second composite layer. The first composite layer and the second composite layer each include a first dielectric layer and a second dielectric layer disposed opposite to and in contact with each other, the first dielectric layer is in contact with the metal trace, and a stiffness of the second dielectric layer is greater than a stiffness of the first dielectric layer.
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公开(公告)号：US10903135B2
公开(公告)日：2021-01-26
申请号：US15855752
申请日：2017-12-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： HuiLi Fu , Shujie Cai , Xiao Hu
IPC: H01L23/373 , H01L25/00 , H01L25/065 , H01L23/31 , H01L21/48 , H01L23/538 , H01L23/00
Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.
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公开(公告)号：US20130221537A1
公开(公告)日：2013-08-29
申请号：US13754515
申请日：2013-01-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： HuiLi Fu , Ting Lei , Xiaowei Wang , Nan Zhao
IPC: H01L23/498
CPC classification number: H01L23/49827 , H01L23/147 , H01L23/49816 , H01L23/50 , H01L25/0657 , H01L2224/16 , H01L2224/48091 , H01L2225/06513 , H01L2225/06541 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
Abstract: A semiconductor device is provided in the present invention. The semiconductor device includes a silicon substrate, configured to bear a chip; a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; and an interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip. With the semiconductor device according to the embodiments of the present invention, the power supply voltage can be directly sent from the silicon substrate to the chip after being generated, thereby shortening the power supply link and reducing the power supply/ground noise.
Abstract translation: 在本发明中提供半导体器件。 半导体器件包括被配置为承载芯片的硅衬底; 布置在所述硅衬底内的电源管理模块，被配置为将电源电压转换为所述芯片所需的输入电压; 以及互连系统，被配置为接收电源电压，将电源电压发送到电源管理模块，并将输入电压传送到芯片。 利用根据本发明的实施例的半导体器件，可以在生成之后将电源电压从硅衬底直接发送到芯片，从而缩短电源链路并降低电源/接地噪声。
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公开(公告)号：US10784181B2
公开(公告)日：2020-09-22
申请号：US15905044
申请日：2018-02-26
Applicant: Huawei Technologies Co., Ltd.
Inventor： HuiLi Fu , Jyh Rong Lin , Shujie Cai
IPC: H01L23/373 , H01L23/42 , H01L21/48 , H01L23/367
Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.
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Patent Agency Ranking
公开(公告)号：US10693233B2
公开(公告)日：2020-06-23
申请号：US16049104
申请日：2018-07-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liangsheng Liu , Xinhong Li , HuiLi Fu
Abstract: A patch antenna unit and an antenna that relate to the field of communications technology wherein the patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.
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公开(公告)号：US20180337456A1
公开(公告)日：2018-11-22
申请号：US16049104
申请日：2018-07-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liangsheng Liu , Xinhong Li , HuiLi Fu
Abstract: A patch antenna unit and an antenna that relate to the field of communications technology wherein the patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.
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公开(公告)号：US11189927B2
公开(公告)日：2021-11-30
申请号：US16872920
申请日：2020-05-12
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liangsheng Liu , Xinhong Li , HuiLi Fu
Abstract: A patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.
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公开(公告)号：US10727595B2
公开(公告)日：2020-07-28
申请号：US16049104
申请日：2018-07-30
Applicant: Huawei Technologies Co., Ltd.
Inventor： Liangsheng Liu , Xinhong Li , HuiLi Fu
Abstract: A patch antenna unit and an antenna that relate to the field of communications technology wherein the patch antenna unit includes a first support layer, a substrate, a second support layer, and an integrated circuit that are stacked. One radiation patch is attached to the first support layer, and one radiation patch is attached to the second support layer. A ground layer is disposed on the second support layer, a coupling slot is disposed on the ground layer, and a feeder corresponding to the coupling slot is disposed on the second support layer. The integrated circuit is connected to the first ground layer and the feeder. In the foregoing specific technical solution, a four-layer substrate is used for fabrication.
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公开(公告)号：US20180190569A1
公开(公告)日：2018-07-05
申请号：US15855752
申请日：2017-12-27
Applicant: Huawei Technologies Co., Ltd.
Inventor： HuiLi Fu , Shujie Cai , Xiao Hu
IPC: H01L23/373 , H01L23/538 , H01L23/00 , H01L21/48
CPC classification number: H01L23/3735 , H01L21/4853 , H01L21/4871 , H01L23/3135 , H01L23/373 , H01L23/538 , H01L24/16 , H01L24/48 , H01L25/0655 , H01L25/50 , H01L2224/16225 , H01L2224/48225 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/00012 , H01L2224/45099
Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.
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